ISL6333_14 Datasheet, PDF (30/40 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with Integrated MOSFET Drivers and Light Load Efficiency Enhancements for Intel VR11.1 Applications

ISL6333, ISL6333A, ISL6333B, ISL6333C
pulls the output voltage below a level that might cause
damage to the load. The LGATE outputs remain high until
VDIFF falls 110mV below the OVP threshold that tripped the
overvoltage protection circuitry. The controllers will continue
to protect the load in this fashion as long as the overvoltage
condition recurs. Once an overvoltage condition ends the
controllers latch off, and must be reset by toggling EN, or
through POR, before a soft-start can be reinitiated.
There is an OVP condition that exists that will not latch off the
controllers. During a soft-start sequence, if the VDIFF voltage is
above the OVP threshold an overvoltage event will occur, but
will be released once VDIFF falls 110mV below the OVP
threshold. If VDIFF then rises above the OVP trip threshold a
second time, the controllers will be latched off and cannot be
restarted until the controllers are reset.
Pre-POR Overvoltage Protection
Prior to the controller and driver bias pins exceeding their
POR levels, the controllers are designed to protect the load
from any overvoltage events that may occur. This is
accomplished by means of an internal 10kΩ resistor tied from
PHASE to LGATE, which turns on the lower MOSFET to
control the output voltage until the overvoltage event ceases
or the input power supply cuts off. For complete protection,
the low side MOSFET should have a gate threshold well
below the maximum voltage rating of the load/microprocessor.
In the event that during normal operation the controller or
driver bias voltages fall back below their POR threshold, the
pre-POR overvoltage protection circuitry reactivates to
protect from any more pre-POR overvoltage events.
Undervoltage Detection
The undervoltage threshold is set at DAC*0.50V of the VID
code. When the output voltage (VDIFF) is below the
undervoltage threshold, VR_RDY gets pulled low. No other
action is taken by the controllers. VR_RDY will return high if
the output voltage rises above DAC*0.60V.
Open Sense Line Prevention
In the case that either of the remote sense lines, VSEN or
GND, become open, the controllers are designed to prevent
the regulator from regulating. This is accomplished by
means of a small 5µA pull-up current on VSEN, and a
pull-down current on RGND. If the sense lines are opened at
any time, the voltage difference between V_SEN and R_GND
will increase until an overvoltage event occurs, at which
point overvoltage protection activates and the controllers
stop regulating. The controllers will be latched off and cannot
be restarted until they are reset.
Overcurrent Protection
The controllers take advantage of the proportionality
between the load current and the average current, I_AVG, to
detect an overcurrent condition. Two different methods of
detecting overcurrent events are available on the controllers.
The first method continually compares the average sense
current with a constant 100µA OCP reference current, as
shown in Figure 18. Once the average sense current
exceeds the OCP reference current, a comparator triggers
the converter to begin overcurrent protection procedures.
For this first method the overcurrent trip threshold is dictated
by the DCR of the inductors, the number of active channels,
and the RSET pin resistor, R_SET. To calculate the overcurrent
trip level, I_OCP, using this method use Equation 22, where N is
the number of active channels, DCR is the individual
inductor’s DCR, and R_SET is the RSET pin resistor value.
I_OCP = -¹---⁰---⁰-----^â‹---¹---_D0----^–-_C--⁶---_R-^â‹---^R--_â‹---₄^S---₀-^E--₀--^T----^â‹---^N------^â‹---³--
(EQ. 22)
During VID-on-the-fly transitions the overcurrent trip level for
this method is boosted to prevent false overcurrent trip
events that can occur. Starting from the beginning of a
dynamic VID transition, the overcurrent trip level is boosted
to 140µA. The OCP level will stay at this boosted level until
50µs after the end of the dynamic VID transition, at which
point it will return to the typical 100µA trip level.
The second method for detecting overcurrent events
continuously compares the voltage on the IMON pin, V_IMON,
to the overcurrent protection voltage, V_OCP, as shown in
Figure 18. The average channel sense current flows out the
IMON pin and through R_IMON, creating the IMON pin
voltage which is proportional to the output current. When the
IMON pin voltage exceeds the V_OCP voltage threshold, the
overcurrent protection circuitry activates. Since the IMON pin
voltage is proportional to the output current, the overcurrent
trip level, I_OCP, can be set by selecting the proper value for
R_IMON, as shown in Equation 23.
I_OCP
=
-³----^â‹---^V-----^O----^C----^P-----^â‹---^R-----^S----^E----^T----^â‹---^N---
DCR ⋅ R_IOUT ⋅ 400
(EQ. 23)
Once the output current exceeds the overcurrent trip level,
V_IMON will exceed V_OCP and a comparator will trigger the
converter to begin overcurrent protection procedures.
At the beginning of an overcurrent shutdown, the controllers
turn off both upper and lower MOSFETs and lowers
VR_RDY. The controllers will then attempt to soft-start after a
delay of typically 8xTD1. If the overcurrent fault remains, the
trip-retry cycles will continue until either the controller is
disabled or the fault is cleared. Note that the energy
delivered during trip-retry cycling is much less than during
full-load operation, so there is no thermal hazard.
30
FN6520.3
October 8, 2010