ISL6333_14 Datasheet, PDF (32/40 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with Integrated MOSFET Drivers and Light Load Efficiency Enhancements for Intel VR11.1 Applications

ISL6333, ISL6333A, ISL6333B, ISL6333C
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 26,
the required time for this commutation is t₁ and the
approximated associated power loss is P_UP(1).
P_UP(1) ≈ V_IN
⋅
⎛
⎝
I--_M---
N
+
I--_{P--2-----P--⎠⎞}
⋅
⎛
⎜
t--_1--
⎞
⎟
⎝ ²âŽ 
⋅ f_S
(EQ. 26)
At turn-on, the upper MOSFET begins to conduct and this
transition occurs over a time t₂. In Equation 27, the
approximate power loss is P_UP(2).
P_UP(2)
≈
V_IN
⋅
⎛
⎜
-I-^M---
⎝^N
–
I--_{P-------P--⎟⎞}
2_⎠
⋅
⎛
⎜
⎝
-t-²--
⎞
⎟
2_⎠
⋅
f_S
(EQ. 27)
A third component involves the lower MOSFET
reverse-recovery charge, Q_rr. Since the inductor current has
fully commutated to the upper MOSFET before the
lower-MOSFET body diode can recover all of Q_rr, it is
conducted through the upper MOSFET across VIN. The
power dissipated as a result is P_UP(3) shown in Equation 28.
P_UP(3) = V_IN ⋅ Q_rr ⋅ f_S
(EQ. 28)
Finally, the resistive part of the upper MOSFET is given in
Equation 29 as P_UP(4)..
P_UP(4) ≈ r_DS(ON) ⋅ d ⋅
⎛
⎜
⎝
I--_{M---⎟⎞}
N⎠
2
+
I--_P-------P--²
12
(EQ. 29)
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 26, 27, 28 and 29. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controllers. Since there are a total of three
drivers in the controller package, the total power dissipated
by all three drivers must be less than the maximum
allowable power dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 7x7 QFN package is approximately 3.5W
at room temperature. See “Layout Considerations” on
page 37 for thermal transfer improvement suggestions.
When designing the controllers into an application, it is
recommended that the following calculation is used to ensure
safe operation at the desired frequency for the selected
MOSFETs. The total gate drive power losses, P_{Qg_TOT}, due to
the gate charge of MOSFETs and the integrated driver’s
internal circuitry and their corresponding average driver current
can be estimated with Equations 30 and 31, respectively.
P_{Qg_TOT} = P_{Qg_Q1} + P_{Qg_Q2} + I_Q ⋅ VCC
(EQ. 30)
P _{Q g _Q1}
=
3_--
2
⋅
Q_G
1
⋅
PV
C
C
⋅
F_S
W
⋅
N_Q1
⋅
N_PHA
S
E
P_{Qg_Q2} = Q_G2 ⋅ PVCC ⋅ F_SW ⋅ N_Q2 ⋅ N_PHASE
(EQ. 31)
I_DR
=
⎛
⎝
3_--
2
⋅
Q_G1
⋅
N
Q
1
+
Q_G
2
⋅
N_Q
⎞
2⎠
⋅ N_PHASE ⋅ F_SW + I_Q
In Equations 30 and 31, P_{Qg_Q1} is the total upper gate drive
power loss and P_{Qg_Q2} is the total lower gate drive power
loss; the gate charge (Q_G1 and Q_G2) is defined at the
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; I_Q is the driver total
quiescent current with no load at both drive outputs; N_Q1 and
N_Q2 are the number of upper and lower MOSFETs per phase,
respectively; N_PHASE is the number of active phases. The
I_Q*VCC product is the quiescent power of the controller
without capacitive load and is typically 75mW at 300kHz.
PVCC
BOOT
D
R_HI1
R_LO1
UGATE
C_GD
G
R_G1
R_GI1
C_GS
S
C_DS
Q₁
PHASE
FIGURE 20. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
R_HI2
R_LO2
LGATE
C_GD
G
R_G2
R_GI2
C_GS
S
D
C_DS
Q₂
FIGURE 21. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
32
FN6520.3
October 8, 2010