ISL6333_14 Datasheet, PDF (29/40 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with Integrated MOSFET Drivers and Light Load Efficiency Enhancements for Intel VR11.1 Applications

ISL6333, ISL6333A, ISL6333B, ISL6333C
ramp times, t_d2 and t_d4, can be calculated based on
Equations 20 and 21:
t_d2 = 1.1 ⋅ R_SS ⋅ 8 ⋅ 10^–3(μs)
(EQ. 20)
t_d4 = V_VID – 1.1 ⋅ R_SS ⋅ 8 ⋅ 10^–3(μs)
(EQ. 21)
For example, when VID is set to 1.5V and the R_SS is set at
100kΩ, the first soft-start ramp time t_d2 will be 880µs and the
second soft-start ramp time t_d4 will be 320µs.
After the DAC voltage reaches the final VID setting, VR_RDY
will be set to high with the fixed delay t_d5. The typical value for
t_d5 is 93µs.
OUTPUT PRECHARGED
ABOVE DAC LEVEL
OUTPUT PRECHARGED
BELOW DAC LEVEL
GND>
V_OUT (0.5V/DIV)
GND>
EN (5V/DIV)
t1 t2
t3
FIGURE 17. SOFT-START WAVEFORMS FOR ISL6333-BASED
MULTI-PHASE CONVERTER
Pre-Biased Soft-Start
The controllers also have the ability to start up into a
pre-charged output, without causing any unnecessary
disturbance. The FB pin is monitored during soft-start, and
should it be higher than the equivalent internal ramping
reference voltage, the output drives hold both MOSFETs off.
Once the internal ramping reference exceeds the FB pin
potential, the output drives are enabled, allowing the output to
ramp from the pre-charged level to the final level dictated by
the DAC setting. Should the output be pre-charged to a level
exceeding the DAC setting, the output drives are enabled at
the end of the soft-start period, leading to an abrupt correction
in the output voltage down to the DAC-set level.
Fault Monitoring and Protection
The controllers actively monitor the output voltage and current
to detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common VR_RDY indicator is provided for linking to external
system monitors. The schematic in Figure 18 outlines the
interaction between the fault monitors and the VR_RDY signal.
VR_RDY Signal
The VR_RDY pin is an open-drain logic output that signals
whether or not the controllers are regulating the output
voltage within the proper levels, and whether any fault
conditions exist. This pin should be tied through a resistor to
a voltage source that’s equal to or less then VCC.
I_AVG
100µA
+
OCP
-
DAC
+175mV
1.280V
+
OCL
-
I₁
140µA
REPEAT FOR
EACH CHANNEL
+
OCP
-
IMON
V_OCP
SOFT-START, FAULT
AND CONTROL LOGIC
VDIFF
0.50xDAC
-
OVP
+
-
UV
+
VR_RDY
ISL6333 INTERNAL CIRCUITRY
FIGURE 18. POWER GOOD AND PROTECTION CIRCUITRY
VR_RDY indicates whether VDIFF is within specified
overvoltage and undervoltage limits after a fixed delay from the
end of soft-start. VR_RDY transitions low when an
undervoltage, overvoltage, or overcurrent condition is detected
or when the controllers are disabled by a reset from EN, POR,
or one of the no-CPU VID codes. In the event of an overvoltage
or overcurrent condition, or a no-CPU VID code, the controllers
latch off and VR_RDY will not return high until EN is toggled
and a successful soft-start is completed. In the case of an
undervoltage event, VR_RDY will return high when the output
voltage rises above the undervoltage hysteresis level. VR_RDY
is always low prior to the end of soft-start.
Overvoltage Protection
The controllers constantly monitor the difference between the
VSEN and RGND voltages to detect if an overvoltage event
occurs. During soft-start, while the DAC is ramping up, the
overvoltage trip level is the higher of a fixed voltage 1.280V or
DAC + 175mV. Upon successful soft-start, the overvoltage trip
level is only DAC + 175mV. When the output voltage rises
above the OVP trip level actions are taken by the controllers to
protect the microprocessor load.
At the inception of an overvoltage event, LGATE1, LGATE2,
and LGATE3 are commanded high and the VR_RDY signal
is driven low. This turns on the all of the lower MOSFETs and
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FN6520.3
October 8, 2010