ISL6333_14 Datasheet, PDF (27/40 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with Integrated MOSFET Drivers and Light Load Efficiency Enhancements for Intel VR11.1 Applications

ISL6333, ISL6333A, ISL6333B, ISL6333C
.
EXTERNAL CIRCUIT
+12V
1.0µF
PVCC1
ISL6333, ISL6333B INTERNAL CIRCUIT
GVOT
REG.
SET BY STATE
OF PSI# AND
SS PINS
BYP1
1.0µF
LVCC1
+12V
PVCC2_3
1.0µF
LVCC2, LVCC3
+5V TO
+12V
PUVCC
1.0µF
UVCC1, UVCC2,
UVCC3
LVCC = LOWER GATE DRIVE
UVCC = UPPER GATE DRIVE
FIGURE 12. INTERNAL GATE DRIVE CONNECTIONS AND
GAVE VOLTAGE OPTIMIZATION (GVOT)
Gate Voltage Optimization Technology (GVOT)
(ISL6333, ISL6333B Only)
The ISL6333 and ISL6333B are designed to optimize the
Channel 1 lower MOSFET gate drive voltage to ensure high
efficiency in both normal and low power states. In the normal
power state when the converter load current is high, the
conduction losses of the lower MOSFETs play a large role in
the overall system efficiency. In normal power state, the
lower gate drive voltage should be higher to decrease the
conduction losses of the lower MOSFETs and increase the
system efficiency. In the low power state, where the
converter load current is significantly smaller, MOSFET
driving loss becomes a much higher percentage of power
loss associated with the lower MOSFET. In low power state,
the lower gate drive voltage can therefore be reduced to
decrease the driving losses of the lower MOSFETs and
increase the system efficiency.
This gate drive voltage optimization is accomplished by an
internal linear regulator that regulates the Channel 1 lower
gate drive voltage, LVCC1, to certain levels depending on
the state of the PSI# and SS pins. The input and output of
this internal regulator is the PVCC1 pin and BYP1 pin,
respectively. The regulator input, PVCC1, should be
connected to a +12V source and decoupled with a quality
1.0µF ceramic capacitor. The regulator output, BYP1, is
internally connected to the lower gate drive of the Channel 1
MOSFET driver, LVCC1. The BYP1 pin should also be
decoupled using a quality 1.0µF ceramic capacitor.
12.0
+40°C THERMAL
11.8
11.6
11.4
11.2
11.0
10.8
10.6
10.4
0
20
40
60
80
100
120
AVERAGE LOAD CURRENT (mA)
FIGURE 13. BYP1, LVCC1 VOLTAGE WHEN PSI# IS HIGH
8.5
+40°C THERMAL
8.0
R_SS TIED TO VCC
7.5
7.0
6.5
6.0
R_SS TIED TO GND
5.5
5.0
0
20
40
60
80
100
120
AVERAGE LOAD CURRENT (mA)
FIGURE 14. BYP1, LVCC1 VOLTAGE WHEN PSI# IS LOW
As Figures 13 and 14 illustrate, the internal regulator has
been designed so that its output voltage, BYP1, is dependent
upon the average load current. In the normal power state,
when PSI# is high, the ISL6333 and ISL6333B regulate BYP1
to around 11.2V at a 50mA average load current. In the low
power state, when PSI# is low, BYP1 is regulated down to one
of two voltages depending on the state of the SS pin. If the SS
pin is tied to ground through the R_SS resistor, BYP1 is
regulated down to 5.75V at a 50mA average load current. If
the SS pin is tied to VCC through the R_SS resistor, BYP1 is
regulated down to 7.75V at a 50mA average load current.
It is possible to disable the internal GVOT regulator by shorting
the PVCC1 pin to the BYP1 pin. This essentially bypasses the
internal regulator setting the Channel 1 lower gate drive
voltage, LVCC1, to the voltage input on the PVCC1 pin.
27
FN6520.3
October 8, 2010