ISL59450 Datasheet, PDF (33/37 Pages) Intersil Corporation – Multiformat Video Crosspoint with Integrated Sync Separator

ISL59450
PARAMETER
td_HOUT
t_HOUT
DESCRIPTION
HOUT Timing Relative to Input
Horizontal Output Width
Sync Separator HSYNC Timing for 720p
CONDITIONS: V_D = 3.3V T_A = +25°C
CONDITIONS
SYNCIN
TYP
UNIT
200
ns
5
µs
H_OUT
td_HOUT
t_HOUT
PARAMETER
td_HOUT
t_HOUT
DESCRIPTION
HOUT Timing Relative to Input
Horizontal Output Width
ISL59450 Serial Communications
I²C Overview
The ISL59450 uses a 2-wire I²C serial bus for
communication with its host. SCL is the Serial Clock line,
driven by the host, and SDA is the Serial Data line, which
can be driven by all devices on the bus. SDA is open drain to
allow multiple devices to share the same bus
simultaneously.
Communication is accomplished in three steps:
1. The Host selects the ISL59450 with which it wishes to
communicate.
2. The Host writes the initial ISL59450 Configuration
Register address it wishes to write to or read from.
3. The Host writes to or reads from the ISL59450’s
Configuration Register. The ISL59450’s internal address
pointer auto increments, so to read registers 0x00
through 0x16, for example, one would write 0x00 in step
two, then repeat step four 28 times, with each read
returning the next register value.
The ISL59450 has a 7-bit address on the serial bus. The upper
6-bits are permanently set to 100010x, with the x determined by
the state of the Address pin (Table 3). This allows two
33
CONDITIONS
TYP
@ 3.3V
90
1.90
UNIT
ns
µs
ISL59450s to be independently controlled while sharing the
same bus. The Address pin has an internal pull-down resistor
to pull the terminal low to set a zero.
TABLE 3. I²C ADDRESS OPTIONS
B7 B6 B5 B4 B3 B2
B1
B0 HEX
A6
A0
(MSB) A5 A4 A3 A2 A1 (Address) R/W
1
0 0 0 01
0
1/0 0x85/0x84
1
0 0 0 01
1
1/0 0x87/0x86
The bus is nominally inactive, with SDA and SCL high.
Communication begins when the host issues a START
command by taking SDA low while SCL is high (Figure 34).
The ISL59450 continuously monitors the SDA and SCL lines
for the start condition and will not respond to any command
until this condition has been met. The host then transmits the
7-bit serial address plus a R/W bit, indicating if the next
transaction will be a Read (R/W = 1) or a Write (R/W = 0). If
the address transmitted matches that of any device on the
bus, that device must respond with an ACKNOWLEDGE
(Figure 35).
FN7510.0
February 14, 2008