ISL59450 Datasheet, PDF (25/37 Pages) Intersil Corporation – Multiformat Video Crosspoint with Integrated Sync Separator

Register Descriptions
ADDRESS
REGISTER
0x00
Sync Separator A
ISL59450
BIT(S) FUNCTION NAME
DESCRIPTION
1:0 Input Select A
Chooses the sync source for Sync Separator A to
process. Use these bits in conjunction with the Sync
Type bit directly below.
00: Component SOG (Channel A)
01: S-Video SOG (Channel A)
10: Composite SOG (Channel A)
11: External H and V or CSYNC on H (Channel A)
2 Sync Type A
This bit must be set to the type of incoming sync. For all
SOG or CSYNC signals, this bit should be set.
0: HSYNC is on HSYNCA, VSYNC is on VSYNCA
1: SOG or CSYNC on HSYNCA
3 Sync Input Polarity A This bit must be set depending on the polarity of the
incoming sync.
0: SOG and active low external HSYNC/CSYNC.
1: Active high external, HSYNC/CSYNC signal.
This forces the internal polarity of the HSYNC signal to
be correct for clamping. Please note setting this bit also
inverts the polarity of HsyncA and VsyncA outputs. See
“Typical Register Settings” on page 31 for correct
values.
4 Reserved
Set this bit to 0.
5 Enable A
0: Sync Separator A is disabled
1: Sync Separator A is enabled
6 Reserved
Set this bit to 0.
7 Sync Output Polarity A Polarity of HsyncA and VsyncA outputs
0: Active Low
1: Active High
Note: If the Field Invert Enable bit (register 0x14b1) is
set, FieldA’s output will also be inverted when this bit is
set.
25
FN7510.0
February 14, 2008