ISL59450 Datasheet, PDF (14/37 Pages) Intersil Corporation – Multiformat Video Crosspoint with Integrated Sync Separator

ISL59450
Pin Descriptions (Continued)
PIN NUMBER
PIN NAME
DESCRIPTION
120
V_LUMAx2_INA
119
V_LUMAx1_INA
118
VSLICE_INA
117
VTIP_INA
Analog Input. Luma Reference Level for DC-Restore when A_V = 2, for Channel A. When using the YPbPr
inputs in RGB mode, this DC voltage sets the clamp voltage of the Pr/R and Pb/B signals for Channel A
when the gain is set to x2. When using the YPbPr inputs in YPbPr mode, this DC voltage sets the clamp
voltage of the Pr/R and Pb/B signals for Channel A.This input is typically tied together with V_LUMAx2_INB
and driven with the same voltage. The Y/G signal is clamped to the VTIP_INA voltage in master mode and
V_LUMAx2_INA in slave mode.
Analog Input. Luma Reference Level for DC-Restore when A_V = 1, for Channel A. When using the YPbPr
inputs in RGB mode, this DC voltage sets the clamp voltage of the R and B signals for Channel A when
the gain is set to x1. This input is typically tied together with V_LUMAx1_INB and driven with the same voltage.
The Y/G signal is clamped to the VTIP_INA voltage in master mode and V_LUMAx1_INA in slave mode.
Analog Input. Slicer comparator threshold for extracting composite sync from video, for Channel A. This DC
voltage is typically set to 0.07V above VTIP_INA, creating a sync tip slicing level of 70mV. This input is
typically tied together with VSLICE_INB and driven with the same voltage.
Analog Input. Sync Tip Reference Level for DC-Restore, for Channel A. This DC voltage sets the level of
the sync tip of Channel A’s output signal. This input is typically tied together with VTIP_INB and driven with
the same voltage. In RGB mode (with no Sync-on-Green), this sets the black level of the G channel.
45
V_CHROMAx2_INB
Analog Input. Chroma Reference Level for DC-Restore when A_V = 2, for Channel A. This DC voltage sets
the midpoint voltage of the C signal (S-Video) and the Pb, Pr signals (Component video) for Channel A when
the gain is set to x2. When using the YPbPr inputs in YPbPr mode, this DC voltage sets the clamp voltage
of the Pr/R and Pb/B signals for Channel B. This input is typically tied together with V_CHROMAx2_INA and
driven with the same voltage.
46
V_CHROMAx1_INB
Analog Input. Chroma Reference Level for DC-Restore when A_V = 1, for Channel A. This voltage sets the
midpoint voltage of the C signal (S-Video) and the Pb, Pr signals (Component video) for Channel A when
the gain is set to x1. When using the YPbPr inputs in YPbPr mode, this DC voltage sets the clamp voltage
of the Pr/R and Pb/B signals for Channel B. This input is typically tied together with V_CHROMAx1_INA and
driven with the same voltage.
47
V_LUMAx2_INB
48
V_LUMAx1_INB
49
VSLICE_INB
50
VTIP_INB
I²C CONTROL AND I/O
85
SDA
82
SCL
92
Address
Analog Input. Luma Reference Level for DC-Restore when A_V = 2, for Channel B. When using the YPbPr
inputs in RGB mode, this DC voltage sets the clamp voltage of the R and B signals for Channel B when
the gain is set to x2. This input is typically tied together with V_LUMAx2_INA and driven with the same voltage.
The Y/G signal is clamped to the VTIP_INB voltage in master mode and V_LUMAx2_INB in slave mode.
Analog Input. Luma Reference Level for DC-Restore when A_V = 1, for Channel B. When using the YPbPr
inputs in RGB mode, this DC voltage sets the clamp voltage of the R and B signals for Channel B when
the gain is set to x1. This input is typically tied together with V_LUMAx1_INA and driven with the same voltage.
The Y/G signal is clamped to the VTIP_INB voltage in master mode and V_LUMAx1_INB in slave mode.
Analog Input. Slicer comparator threshold for extracting composite sync from video, for Channel B. This DC
voltage is typically set to 0.07V above VTIP_INB, creating a sync tip slicing level of 70mV. This input is
typically tied together with VSLICE_INA and driven with the same voltage.
Analog Input. Sync Tip Reference Level for DC-Restore, for Channel B. This DC voltage sets the level of
the sync tip of Channel B’s output signal. This input is typically tied together with VTIP_INA and driven with
the same voltage. In RGB mode (with no Sync-on-Green), this sets the black level of the G channel.
I²C Bus Data I/O
I²C Bus Clock
Digital Input with internal pull-down. Sets I²C address: 0x84 if tied low, 0x8C if tied high. (300k pull-down)
IC RESET, ENABLE AND MISC.
77
Reset
5V Digital Input, with 3.5V logic threshold and a 300k pull-down. Tie to +5V for normal operation. Taking
Reset to 0V and back to 5V initializes all data registers to 0x00.
90
PowerDown
Digital Input with 300k pull-down. When this pin is taken high, all analog circuitry is disabled to minimize
power consumption. In PowerDown mode, the outputs are tri-stated while the I²C interface remains active
and all register data is retained.
POWER SUPPLIES
18, 20, 42, 125 V_A
+5V Analog supply
14
FN7510.0
February 14, 2008