X55060 Datasheet, PDF (3/23 Pages) Intersil Corporation – Dual Voltage Monitor with Integrated System Battery Switch and EEPROM

X55060
PIN DESCRIPTION
Pin Name
Function
1
CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance
state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode.
CS LOW enables the device, placing it in the active power mode. Prior to the start of any opera-
tion after power-up, a HIGH to LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The
absence of a HIGH to LOW transition within the watchdog time out period results in RESET/RESET
going active.
2
NC
No internal connections
3
SO
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
4
RESET Reset Output. RESET is an active HIGH, open drain output which is the inverse of the RESET
output.
5 LOWLINE Low V_CC Detect. This open drain output signal goes LOW when V_CC < V_TRIP1 and
immediately goes HIGH when V_CC > V_TRIP1. This pin goes LOW 250ns before RESET pin.
6
V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than V_TRIP2
and goes HIGH when V2MON exceeds V_TRIP2. There is no power-up reset delay circuitry on this
pin.
7
V2MON V2 Voltage Monitor Input. When the V2MON input is less than the V_TRIP2 voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V_SS or V_CC
when not used.
8
WP
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the Watchdog Timer control and the memory write protect bits.
9
NC
No internal connections
10
V_SS
Ground
11
SI
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on
this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
12
NC
No internal connections
13
NC
No internal connections
14
SCK Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising
edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of
SCK changes the data output on the SO pin.
15
V_BATT Battery Supply Voltage. This input provides a backup supply in the event of a failure of the pri-
mary V_CC voltage. The V_BATT voltage typically provides the supply voltage necessary to maintain
the contents of SRAM and also powers the internal logic to “stay awake.” If unused connect
V_BATT to ground.
3
FN8133.0
March 28, 2005