X55060 Datasheet, PDF (11/23 Pages) Intersil Corporation – Dual Voltage Monitor with Integrated System Battery Switch and EEPROM

X55060
When WP is HIGH, all functions, including nonvolatile
writes to the Status Register operate normally. Setting
the WPEN bit in the Status Register to “0” blocks the
WP pin function, allowing writes to the Status Register
when WP is HIGH or LOW. Setting the WPEN bit to
“1” while the WP pin is LOW activates the Programma-
ble ROM mode, thus requiring a change in the WP pin
prior to subsequent Status Register changes. This
allows manufacturing to install the device in a system
with WP pin grounded and still be able to program the
Status Register. Manufacturing can then load Configu-
ration data, manufacturing time and other parameters
into the EEPROM, then set the portion of memory to
be protected by setting the block lock bits, and finally
set the “OTP mode” by setting the WPEN bit. Data
changes to protected areas of the device now require
a hardware change.
Read Sequence
When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
16-bit address. After the READ opcode and address
are sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored in
memory at the next address can be read sequentially
by continuing to provide clock pulses. The address is
automatically incremented to the next higher address
after each byte of data is shifted out. The read operation
is terminated by taking CS high. Refer to the Read
EEPROM Array Sequence (Figure 7).
To read the Status Register, the CS line is first pulled
low to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the contents
of the Status Register are shifted out on the SO line.
Refer to the Read Status Register Sequence (Figure 8).
Refer to the Serial Output Timing on page 18.
Write Sequence
Prior to any attempt to write data into the device, the
“Write Enable” Latch (WEL) must first be set by issu-
ing the WREN instruction (Figure 9). CS is first taken
LOW, then the WREN instruction is clocked into the
device. After all eight bits of the instruction are trans-
mitted, CS must then be taken HIGH. If the user con-
tinues the Write Operation without taking CS HIGH
after issuing the WREN instruction, the Write Opera-
tion will be ignored.
To write data to the EEPROM memory array, the user
then issues the WRITE instruction followed by the 16
bit address and then the data to be written. Any
unused address bits are specified to be “0’s”. The
WRITE operation minimally takes 32 clocks. CS must
go low and remain low for the duration of the opera-
tion. If the address counter reaches the end of a page
and the clock continues, the counter will roll back to
the first address of the page and overwrite any data
that may have been previously written.
For the Page Write Operation (byte or page write) to
be completed, CS can only be brought HIGH after bit 0
of the last data byte to be written is clocked in. If it is
brought HIGH at any other time, the write operation
will not be completed (Figure 10).
To write to the Status Register, the WRSR instruction
is followed by the data to be written (Figure 11).
While the write is in progress following a Status Regis-
ter or EEPROM Sequence, the Status Register may
be read to check the WIP bit. During this time the WIP
bit will be high. Refer to Serial Input timing on page 17.
OPERATIONAL NOTES
The device powers-up in the following state:
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– SO pin is high impedance.
– The Write Enable Latch is reset.
– Reset Signal is active for t_PURST.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– A WREN instruction must be issued to set the Write
Enable Latch.
– A valid write command and address must be sent to
the device.
– CS must come HIGH after a multiple of 8 data bits in
order to start a nonvolatile write cycle.
11
FN8133.0
March 28, 2005