X55060 Datasheet, PDF (10/23 Pages) Intersil Corporation – Dual Voltage Monitor with Integrated System Battery Switch and EEPROM

X55060
The Write Enable Latch (WEL) bit indicates the Status
of the Write Enable Latch. When WEL = 1, the latch is
set HIGH and when WEL = 0 the latch is reset LOW.
The WEL bit is a volatile, read only bit. It can be set by
the WREN instruction and can be reset by the WRDS
instruction.
The block lock bits, BL0 and BL1, set the level of block
lock protection. These nonvolatile bits are pro-
grammed using the WRSR instruction and allow the
user to protect one quarter, one half, all or none of the
EEPROM array. Any portion of the array that is block
lock protected can be read but not written. It will
remain protected until the BL bits are altered to disable
block lock protection of that portion of memory.
Status Register Bits Array Addresses Protected
BL1
BL0
X55060
0
0
None (factory setting)
0
1
None
1
0
None
1
1
0000h–1FFFh (All)
The power-on reset time (t_PURST) bit, PUP sets the
initial power or reset time. There are two standard
settings.
PUP
0
1
Time
150 milliseconds (factory settings)
800 milliseconds
Figure 7. Read EEPROM Array Sequence
The Watchdog Timer bits, WD0 and WD1, select the
Watchdog Time-out Period. These nonvolatile bits are
programmed with the WRSR instruction.
Status Register Bits
WD1
WD0
0
0
0
1
1
0
1
1
Watchdog Time Out
(Typical)
800 milliseconds
400 milliseconds
150 milliseconds
disabled (factory setting)
The nonvolatile WPEN bit is programmed using the
WRSR instruction. This bit works in conjunction with
the WP pin to provide an In-Circuit Programmable
ROM function (Table 2). WP tied to V_SS and WPEN bit
programmed HIGH disables all Status Register Write
Operations.
Note 1. Watchdog timer is shipped disabled.
2. The t_PURST time is set to 150ms at the factory.
In Circuit Programmable ROM Mode
This mechanism protects the block lock and Watchdog
bits from inadvertent corruption.
In the locked state (Programmable ROM Mode) the
WP pin is LOW and the nonvolatile bit WPEN is “1”.
This mode disables nonvolatile writes to the device’s
Status Register.
Setting the WP pin LOW while WPEN is a “1” while an
internal write cycle to the Status Register is in progress
will not stop this write operation, but the operation dis-
ables subsequent write attempts to the Status Register.
CS
SCK
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30
Instruction
SI
16 Bit Address
15 14 13
3210
High Impedance
SO
Data Out
7 654321 0
MSB
10
FN8133.0
March 28, 2005