ISL62882_14 Datasheet, PDF (3/42 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6.5™ Mobile CPUs and GPUs

ISL62882, ISL62882B
Functional Pin Descriptions
ISL62882
-
1
ISL62882B
7
2
2
3
3
4
4
5
5
6
6
8
7
9
8
10
9
11
10
11
12
13
14, 15
16
17
18
19
13
14
15
16
17, 18
19
20
22
24
20
25
21
26
22
27
23
28
24
29
-
-
SYMBOL
GND
PGOOD
PSI#
RBIAS
VR_TT#
NTC
VW
COMP
FB
FB2
ISEN2
ISEN1
VSEN
RTN
ISUM- and ISUM+
VDD
VIN
IMON
BOOT1
UGATE1
PHASE1
VSSP1
LGATE1a
LGATE1b
LGATE1
DESCRIPTION
Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin.
Power-Good open-drain output indicating when the regulator is able to supply regulated voltage.
Pull-up externally with a 680Ω resistor to VCCP or 1.9kΩ to 3.3V.
Low load current indicator input. When asserted low, indicates a reduced load current condition.
A resistor to GND sets internal current reference. Use 147kΩ or 47kΩ. The choice of Rbias value,
together with the ISEN2 pin configuration and the external resistance from the COMP pin to GND,
programs the controller to enable/disable the overshoot reduction function and to select the
CPU/GPU mode.
Thermal overload output indicator.
Thermistor input to VR_TT# circuit.
A resistor from this pin to COMP programs the switching frequency (8kΩ gives approximately
300kHz).
This pin is the output of the error amplifier. Also, a resistor across this pin and GND adjusts the
overcurrent threshold.
This pin is the inverting input of the error amplifier.
There is a switch between the FB2 pin and the FB pin. The switch is on in 2-phase mode and is
off in 1-phase mode. The components connecting to FB2 are used to adjust the compensation
in 1-phase mode to achieve optimum performance.
Individual current sensing for Phase 2. When ISEN2 is pulled to 5V VDD, the controller will
disable Phase 2.
Individual current sensing for phase 1.
Remote core voltage sense input. Connect to microprocessor die.
Remote voltage sensing return. Connect to ground at microprocessor die.
Droop current sense input.
5V bias power.
Battery supply voltage, used for feed-forward.
An analog output. IMON outputs a current proportional to the regulator output current.
Connect an MLCC capacitor across the BOOT1 and the PHASE1 pins. The boot capacitor is
charged through an internal boot diode connected from the VCCP pin to the BOOT1 pin, each
time the PHASE1 pin drops below VCCP minus the voltage dropped across the internal boot
diode.
Output of the Phase-1 high-side MOSFET gate driver. Connect the UGATE1 pin to the gate of the
Phase-1 high-side MOSFET.
Current return path for the Phase-1 high-side MOSFET gate driver. Connect the PHASE1 pin to the
node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output
inductor of Phase-1.
Current return path for the Phase-1 low-side MOSFET gate driver. Connect the VSSP1 pin to the
source of the Phase-1 low-side MOSFET through a low impedance path, preferably in parallel
with the traces connecting the LGATE1a and the LGATE1b pins to the gates of the Phase-1
low-side MOSFETs.
Output of the Phase-1 low-side MOSFET gate driver that is always active. Connect the LGATE1a
pin to the gate of the Phase-1 low-side MOSFET that is active all the time.
Another output of the Phase-1 low-side MOSFET gate driver. This gate driver will be pulled low
when the DPRSLPVR pin logic is high. Connect the LGATE1b pin to the gate of the Phase-1
low-side MOSFET that is idle in deeper sleep mode.
Output of the Phase-1 low-side MOSFET gate driver. Connect the LGATE1 pin to the gate of the
Phase-1 low-side MOSFET.
3
FN6890.4
June 21, 2011