ISL62882_14 Datasheet, PDF (18/42 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6.5™ Mobile CPUs and GPUs

ISL62882, ISL62882B
CCM Switching Frequency
The R_fset resistor between the COMP and the VW pins sets the
VW windows size, therefore sets the switching frequency. When
the ISL62882 is in continuous conduction mode (CCM), the
switching frequency is not absolutely constant due to the nature
of the R³â„¢ modulator. As explained in the “Multiphase R³â„¢
Modulator” on page 12, the effective switching frequency will
increase during load insertion and will decrease during load
release to achieve fast response. On the other hand, the
switching frequency is relatively constant at steady state.
Variation is expected when the power stage condition, such as
input voltage, output voltage, load, etc. changes. The variation is
usually less than 15% and doesn’t have any significant effect on
output voltage ripple magnitude. Equation 12 gives an estimate
of the frequency-setting resistor R_fset value. 8kΩ R_fset gives
approximately 300kHz switching frequency. Lower resistance
gives higher switching frequency.
R_fset(kΩ) = (Period(μs) – 0.29) × 2.65
(EQ. 12)
Modes of Operation
TABLE 2. ISL62882 CONFIGURATIONS
ISEN2
Rbias
(kΩ)
CONFIGURATION
OVERSHOOT
REDUCTION
FUNCTION
Connected to the
Power Stage
147 2-phase CPU VR
47
Disabled
Enabled
Tied to 5V
147 1-phase CPU VR
See Table 4
47 1-phase GPU VR
TABLE 3. ISL62882 MODES OF OPERATION
CONFIG.
PSI# DPRSLPVR
OPERATIONAL
MODE
VOLTAGE
SLEW
RATE
2-phase CPU
0
Configuration
0
0
1-phase CCM
1
1-phase DE
5mV/µs
1
0
2-phase CCM
1
1
1-phase DE
1-phase CPU
x
Configuration
0
1-phase CCM
1
1-phase DE
1-phase GPU
x
Configuration
0
1-phase CCM
1
1-phase DE
10mV/µs
The ISL62882 can be configured for 2- or 1-phase operation.
For 1-phase configuration, tie the ISEN2 pin to 5V. In this
configuration, only phase-1 is active.
Table 2 shows the ISL62882 configurations, programmed by the
ISEN2 pin status and the Rbias value.
If the ISEN2 pin is connected to the power stage, the ISL62882 is
in 2-phase CPU VR configuration. Rbias = 147kΩ disables the
overshoot reduction function and Rbias = 47kΩ enables it.
If ISEN2 is tied to 5V, the ISL62882 is configured for 1-phase
operation. Rbias = 147kΩ sets 1-phase CPU VR configuration
and Rbias = 47kΩ sets 1-phase GPU configuration.
Table 3 shows the ISL62882 operational modes, programmed by
the logic status of the PSI# and DPRSLPVR pins.
In 2-phase configuration, the ISL62882 enters 1-phase CCM for
(PSI# = 0 and DPRSLPVR = 0). It drops phase 2 and reduces the
overcurrent and the way-overcurrent protection levels to 1/2 of
the initial values. The ISL62882 enters 1-phase DE mode when
DPRSLPVR = 1 by dropping phase 2.
In 1-phase configuration, the ISL62882 does not change the
operational mode when the PSI# signal changes status. It enters
1-phase DE mode when DLPRSLPVR = 1.
Dynamic Operation
When the ISL62882 is configured for CPU VR application, it
responds to VID changes by slewing to the new voltage at
5mV/µs slew rate. As the output approaches the VID command
voltage, the dv/dt moderates to prevent overshoot. Geyserville-III
transitions commands one LSB VID step (12.5mV) every 2.5µs,
controlling the effective dv/dt at 5mv/µs. The ISL62882 is
capable of 5mV/µs slew rate.
When the ISL62882 is configured for GPU VR application, it
responds to VID changes by slewing to the new voltage at a slew
rate set by the logic status on the DPRSLPVR pin. The slew rate is
5mV/µs when DPRSLPVR = 0 and is doubled when
DPRSLPVR = 1.
When the ISL62882 is in DE mode, it will actively drive the output
voltage up when the VID changes to a higher value. It’ll resume
DE mode operation after reaching the new voltage level. If the
load is light enough to warrant DCM, it will enter DCM after the
inductor current has crossed zero for four consecutive cycles. The
ISL62882 will remain in DE mode when the VID changes to a
lower value. The output voltage will decay to the new value and
the load will determine the slew rate. Over-voltage protection is
blanked during VID down transition in DE mode until the output
voltage is within 60mV of the VID value.
During load insertion response, the Fast Clock function increases
the PWM pulse response speed. The ISL62882 monitors the
VSEN pin voltage and compares it to 100ns-filtered version.
When the unfiltered version is 20mV below the filtered version,
the controller knows there is a fast voltage dip due to load
insertion, hence issues an additional master clock signal to
deliver a PWM pulse immediately.
The R³â„¢ modulator intrinsically has voltage feed-forward. The
output voltage is insensitive to a fast slew rate input voltage
change.
Protections
The ISL62882 provides overcurrent, current-balance,
undervoltage, overvoltage, and over-temperature protections.
The ISL62882 determines overcurrent protection (OCP) by
comparing the average value of the droop current I_droop with an
internal current source threshold. It declares OCP when I_droop is
above the threshold for 120µs. A resistor R_comp from the COMP
pin to GND programs the OCP current source threshold, as well
18
FN6890.4
June 21, 2011