ISL62882_14 Datasheet, PDF (13/42 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6.5™ Mobile CPUs and GPUs

ISL62882, ISL62882B
Since the ISL62882 works with V_crs, which are large amplitude
and noise-free synthesized signals, the ISL62882 achieves lower
phase jitter than conventional hysteretic mode and fixed PWM
mode controllers. Unlike conventional hysteretic mode
converters, the ISL62882 has an error amplifier that allows the
controller to maintain a 0.5% output voltage accuracy.
Figure 7 shows the operation principles during load insertion
response. The COMP voltage rises during load insertion,
generating the master clock signal more quickly, so the PWM
pulses turn on earlier, increasing the effective switching frequency,
which allows for higher control loop bandwidth than conventional
fixed frequency PWM controllers. The VW voltage rises as the
COMP voltage rises, making the PWM pulses wider. During load
release response, the COMP voltage falls. It takes the master clock
circuit longer to generate the next master clock signal so the PWM
pulse is held off until needed. The VW voltage falls as the VW
voltage falls, reducing the current PWM pulse width. This kind of
behavior gives the ISL62882 excellent response speed.
The fact that both phases share the same VW window voltage
also ensures excellent dynamic current balance between phases.
Diode Emulation and Period Stretching
Figure 9 shows the operation principle in diode emulation mode at
light load. The load gets incrementally lighter in the three cases
from top to bottom. The PWM on-time is determined by the VW
window size, therefore is the same, making the inductor current
triangle the same in the three cases. The ISL62882 clamps the
ripple capacitor voltage V_crs in DE mode to make it mimic the
inductor current. It takes the COMP voltage longer to hit V_crs,
naturally stretching the switching period. The inductor current
triangles move further apart from each other such that the
inductor current average value is equal to the load current. The
reduced switching frequency helps to increase light load efficiency.
Vcrs
CCM/DCM BOUNDARY
VW
iL
Vcrs
LIGHT DCM
VW
PHASE
UGATE
iL
Vcrs
DEEP DCM
VW
LGATE
IL
FIGURE 8. DIODE EMULATION
ISL62882 can operate in diode emulation (DE) mode to improve
light load efficiency. In DE mode, the low-side MOSFET conducts
when the current is flowing from source to drain and does not
allow reverse current, emulating a diode. As Figure 8 shows,
when LGATE is on, the low-side MOSFET carries current, creating
negative voltage on the phase node due to the voltage drop
across the ON-resistance. The ISL62882 monitors the current
through monitoring the phase node voltage. It turns off LGATE
when the phase node voltage reaches zero to prevent the
inductor current from reversing the direction and creating
unnecessary power loss.
If the load current is light enough, as Figure 8 shows, the inductor
current will reach and stay at zero before the next phase node
pulse, and the regulator is in discontinuous conduction mode
(DCM). If the load current is heavy enough, the inductor current
will never reach 0A, and the regulator is in CCM although the
controller is in DE mode.
iL
FIGURE 9. PERIOD STRETCHING
Start-up Timing
With the controller's V_DD voltage above the POR threshold, the
start-up sequence begins when VR_ON exceeds the 3.3V logic high
threshold. Figure 10 shows the typical start-up timing when the
ISL62882 is configured for CPU VR application. The ISL62882
uses digital soft-start to ramp-up DAC to the boot voltage of 1.1V at
about 2.5mV/µs. Once the output voltage is within 10% of the
boot voltage for 13 PWM cycles (43µs for frequency = 300kHz),
CLK_EN# is pulled low and DAC slews at 5mV/µs to the voltage set
by the VID pins. PGOOD is asserted high in approximately 7ms.
Similar results occur if VR_ON is tied to V_DD, with the soft-start
sequence starting 120µs after V_DD crosses the POR threshold.
Figure 11 shows the typical start-up timing when the ISL62882 is
configured for GPU VR application. The ISL62882 uses digital
soft start to ramp up DAC to the voltage set by the VID pins. The
slew rate is 5mV/µs when there is DPRSLPVR = 0, and is
doubled when there is DPRSLPVR = 1. Once the output voltage is
within 10% of the target voltage for 13 PWM cycles (43µs for
frequency = 300kHz), CLK_EN# is pulled low. PGOOD is asserted
high in approximately 7ms. Similar results occur if VR_ON is tied
to V_DD, with the soft-start sequence starting 120µs after V_DD
crosses the POR threshold.
13
FN6890.4
June 21, 2011