ISL62882_14 Datasheet, PDF (16/42 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6.5™ Mobile CPUs and GPUs

ISL62882, ISL62882B
COMP
Rdroop
Vdroop
FB
Idroop
Σ ^E/A
DAC
VDAC
INTERNAL
X1
TO IC
VCC_SENSE
VR LOCAL
“CATCH” _VO
RESISTOR
VIDs
VID<0:6>
RTN
VSS
VSS_SENSE
“CATCH”
RESISTOR
FIGURE 12. DIFFERENTIAL SENSING AND LOAD LINE
IMPLEMENTATION
As the load current increases from zero, the output voltage will
droop from the VID table value by an amount proportional to the
load current to achieve the load line. The ISL62882 can sense
the inductor current through the intrinsic DC Resistance (DCR) of
the inductors as shown in Figure 1 or through resistors in series
with the inductors as shown in Figure 2. In both methods,
capacitor C_n voltage represents the inductor total currents. A
droop amplifier converts C_n voltage into an internal current
source with the gain set by resistor R_i. The current source is used
for load line implementation, current monitor and overcurrent
protection.
Figure 12 shows the load line implementation. The ISL62882
drives a current source I_droop out of the FB pin, described by
Equation 1.
I_droop
=
2_----x_----V_---C----n-
R_i
(EQ. 1)
When using inductor DCR current sensing, a single NTC element
is used to compensate the positive temperature coefficient of the
copper winding thus sustaining the load line accuracy with
reduced cost.
I_droop flows through resistor R_droop and creates a voltage drop as
shown in Equation 2.
V_droop = R_droop × I_droop
(EQ. 2)
V_droop is the droop voltage required to implement load line.
Changing R_droop or scaling I_droop can both change the load line
slope. Since I_droop also sets the overcurrent protection level, it is
recommended to first scale I_droop based on OCP requirement,
then select an appropriate R_droop value to obtain the desired
load line slope.
Differential Sensing
Figure 12 also shows the differential voltage sensing scheme.
VCC_SENSE and VSS_SENSE are the remote voltage sensing signals
from the processor die. A unity gain differential amplifier senses
the VSS_SENSE voltage and add it to the DAC output. The error
amplifier regulates the inverting and the non-inverting input
voltages to be equal as shown in Equation 3:
V
C
C_S
EN
S
E
+
V
d
r
o
op
=
V_DAC + VSS_SENSE
(EQ. 3)
Rewriting Equation 3 and substitution of Equation 2 gives:
VCC_SENSE – VSS_SENSE = V_DAC – R_droop × I_droop
(EQ. 4)
Equation 4 is the exact equation required for load line
implementation.
The VCC_SENSE and VSS_SENSE signals come from the processor die.
The feedback will be open circuit in the absence of the processor. As
Figure 12 shows, it is recommended to add a “catch” resistor to feed
the VR local output voltage back to the compensator, and add
another “catch” resistor to connect the VR local output ground to the
RTN pin. These resistors, typically 10Ω~100Ω, will provide voltage
feedback if the system is powered up without a processor installed.
Phase Current Balancing
ISEN2
INTERNAL TO IC
ISEN1
PHASE2
RS
CS
PHASE1
RS
CS
L2
RDCR2 _RPCB2
IL2
VO
L1
RDCR1 _RPCB1
IL1
FIGURE 13. CURRENT BALANCING CIRCUIT
The ISL62882 monitors individual phase average current by
monitoring the ISEN1 and ISEN2 voltages. Figure 13 shows the
current balancing circuit recommended for ISL62882. Each
phase node voltage is averaged by a low-pass filter consisting of
R_s and C_s, and presented to the corresponding ISEN pin. R_s
should be routed to inductor phase-node pad in order to
eliminate the effect of phase node parasitic PCB DCR. Equations
5 and 6 give the ISEN pin voltages:
V_ISEN1 = (R_dcr1 + R_pcb1) × I_L1
(EQ. 5)
V_ISEN2 = (R_dcr2 + R_pcb2) × I_L2
(EQ. 6)
where R_dcr1 and R_dcr2 are inductor DCR; R_pcb1 and R_pcb2 are
parasitic PCB DCR between the inductor output side pad and the
output voltage rail; and I_L1 and I_L2 are inductor average currents.
The ISL62882 will adjust the phase pulse-width relative to the
other phase to make V_ISEN1 = V_ISEN2, thus to achieve I_L1 = I_L2,
when there are R_dcr1 = R_dcr2 and R_pcb1 = R_pcb2.
Using same components for L1 and L2 will provide a good match
of R_dcr1 and R_dcr2. Board layout will determine R_pcb1 and R_pcb2.
It is recommended to have symmetrical layout for the power
delivery path between each inductor and the output voltage rail,
such that R_pcb1 = R_pcb2.
16
FN6890.4
June 21, 2011