ISL62882_14 Datasheet, PDF(22/42 Page) Intersil Corporation – Multiphase PWM Regulator for IMVP-6.5™ Mobile CPUs and GPUs

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ISL62882_14 Datasheet, PDF (22/42 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6.5™ Mobile CPUs and GPUs

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ISL62882, ISL62882B

FIGURE 18. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS

RING

BACK

FIGURE 21. OUTPUT VOLTAGE RING BACK PROBLEM

ISUM+

FIGURE 19. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO SMALL

Rntcs

Rntc

Cn.1

OPTIONAL

Cn.2 Vcn

Ri ISUM-

Rip Cip

FIGURE 20. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO LARGE

For example, given N = 2, Rsum = 3.65kÎ©, Rp = 11kÎ©,

Rntcs = 2.61kÎ©, Rntc = 10kÎ©, DCR = 0.88mÎ© and L = 0.36ÂµH,

Equation 19 gives Cn = 0.294ÂµF.

Assuming the compensator design is correct, Figure 18 shows the

expected load transient response waveforms if Cn is correctly

selected. When the load current Icore has a square change, the

output voltage Vcore also has a square response.

If Cn value is too large or too small, VCn(s) will not accurately

represent real-time Io(s) and will worsen the transient response.

Figure 19 shows the load transient response when Cn is too

small. Vcore will sag excessively upon load insertion and may

create a system failure. Figure 20 shows the transient response

when Cn is too large. Vcore is sluggish in drooping to its final

value. There will be excessive overshoot if load insertion occurs

during this time, which may potentially hurt the CPU reliability.

OPTIONAL

FIGURE 22. OPTIONAL CIRCUITS FOR RING BACK REDUCTION

Figure 21 shows the output voltage ring back problem during load

transient response. The load current io has a fast step change, but

the inductor current iL cannot accurately follow. Instead, iL

responds in first order system fashion due to the nature of current

loop. The ESR and ESL effect of the output capacitors makes the

output voltage Vo dip quickly upon load current change. However,

the controller regulates Vo according to the droop current idroop,

which is a real-time representation of iL; therefore it pulls Vo back

to the level dictated by iL, causing the ring back problem. This

phenomenon is not observed when the output capacitor have very

low ESR and ESL, such as all ceramic capacitors.

Figure 22 shows two optional circuits for reduction of the ring back.

Cn is the capacitor used to match the inductor time constant. It

usually takes the parallel of two (or more) capacitors to get the

desired value. Figure 22 shows that two capacitors Cn.1 and Cn.2

are in parallel. Resistor Rn is an optional component to reduce

the Vo ring back. At steady state, Cn.1 + Cn.2 provides the desired

Cn capacitance. At the beginning of io change, the effective

capacitance is less because Rn increases the impedance of the

Cn.1 branch. As Figure 19 explains, Vo tends to dip when Cn is too

small, and this effect will reduce the Vo ring back. This effect is

more pronounced when Cn.1 is much larger than Cn.2. It is also

more pronounced when Rn is bigger. However, the presence of

Rn increases the ripple of the Vn signal if Cn.2 is too small. It is

recommended to keep Cn.2 greater than 2200pF. Rn value

usually is a few ohms. Cn.1, Cn.2 and Rn values should be

determined through tuning the load transient response

waveforms on an actual board.

FN6890.4

June 21, 2011

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