ISL6326B Datasheet, PDF (29/30 Pages) Intersil Corporation – 4-Phase PWM Controller with 8-Bit DAC Code Capable of Precision DCR Differential Current Sensing

ISL6326B
0.6
0.4
0.2
I_L,PP = 0
I_L,PP = 0.5 I_O
I_L,PP = 0.75 I_O
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V_O/V_IN)
FIGURE 20. NORMALIZED INPUT-CAPACITOR RMS
CURRENT vs DUTY CYCLE FOR SINGLE-PHASE
CONVERTER
Layout Considerations
The following layout strategies are intended to minimize the
impact of board parasitic impedances on converter
performance and to optimize the heat-dissipating capabilities
of the printed-circuit board. These sections highlight some
important practices which should not be overlooked during the
layout process.
Component Placement
Within the allotted implementation area, orient the switching
components first. The switching components are the most
critical because they carry large amounts of energy and tend
to generate high levels of noise. Switching component
placement should take into account power dissipation. Align
the output inductors and MOSFETs such that space between
the components is minimized while creating the PHASE
plane. Place the Intersil MOSFET driver IC as close as
possible to the MOSFETs they control to reduce the parasitic
impedances due to trace length between critical driver input
and output signals. If possible, duplicate the same
placement of these components for each phase.
Next, place the input and output capacitors. Position one
high-frequency ceramic input capacitor next to each upper
MOSFET drain. Place the bulk input capacitors as close to
the upper MOSFET drains as dictated by the component
size and dimensions. Long distances between input
capacitors and MOSFET drains result in too much trace
inductance and a reduction in capacitor performance. Locate
the output capacitors between the inductors and the load,
while keeping them in close proximity to the microprocessor
socket.
29
FN9286.0
April 21, 2006