ISL6326B Datasheet, PDF (26/30 Pages) Intersil Corporation – 4-Phase PWM Controller with 8-Bit DAC Code Capable of Precision DCR Differential Current Sensing

ISL6326B
Based on the desired loadline R_LL, the loadline regulation
resistor can be calculated by the following equation:
R_FB
=
N-----R-----_{I--S----E----N----R----L----L-}
R_X
(EQ. 33)
where N is the active channel number, R_ISEN is the sense
resistor connected to the ISEN+ pin, and R_X is the
resistance of the current sense element, either the DCR of
the inductor or R_SENSE depending on the sensing method.
If one or more of the current sense resistors are adjusted for
thermal balance, as in Equation 31, the load-line regulation
resistor should be selected based on the average value of
the current sensing resistors, as given in the following
equation:
∑ ^R_FB
=
R-----_L---L--
R_X
R_ISEN(n)
n
(EQ. 34)
wthheenre_thRIS_{ISEENN+(np)iins.} the current sensing resistor connected to
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in Load-Line Regulation, there are two distinct
methods for achieving these goals.
COMPENSATING LOAD-LINE REGULATED
CONVERTER
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output-filter L-C resonant frequency split with
the introduction of current information into the control loop.
The final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R_C and C_C.
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator by compensating the L-C
poles and the ESR zero of the voltage-mode approximation
yields a solution that is always stable with very close to ideal
transient performance.
C₂ (OPTIONAL)
R_C ^CC
COMP
R_FB
+
V_DROOP
-
FB
VDIFF
FIGURE 16. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6326B CIRCUIT
The feedback resistor, R_FB, has already been chosen as
outlined in Load-Line Regulation Resistor. Select a target
bandwidth for the compensated system, f₀. The target
bandwidth must be large enough to assure adequate
transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of f₀
to the L-C pole frequency and the ESR zero frequency. For
each of the three cases which follow, there is a separate set
of equations for the compensation components.
Case 1:
---------1----------
2π LC
>
f₀
R_C
=
R_F
B
2----π_{----f--0---V-----p---p-------L----C---}
0.75 V _{I N}
C_C
=
--------0---.--7---5----V----^I--^N----------
2πV_PPR_FBf₀
Case 2:
---------1----------
2π LC
≤
f₀
<
--------------1---------------
2πC(ESR)
R_C
=
R_F
B
V-----_P----P----(_--2----π_----)_--²_----f--0--²_{----L----C---}
0.75 V_IN
C_C
=
--------------------0----.-7----5---V-----^I--^N---------------------
(2π)² f₀₂ V_PPR_FB LC
(EQ. 35)
Case 3:
f₀
>
--------------1---------------
2πC(ESR)
R_C
=
R_FB
--------2----^π----f--⁰---V-----^p---^p---L---------
0.75 V_IN (ESR)
C_C
=
-0---.--7---5----V----^I--^N----⁽--E-----S----R-----⁾-------C---
2πV_PPR_FBf₀ L
In Equation 35, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
26
FN9286.0
April 21, 2006