ISL6326B Datasheet, PDF (20/30 Pages) Intersil Corporation – 4-Phase PWM Controller with 8-Bit DAC Code Capable of Precision DCR Differential Current Sensing

ISL6326B
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to validate the VID input is 500ns.
Therefore the minimum TD3 is about 86µs.
During TD2 and TD4, ISL6326B digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which
is defined by the resistor R_SS from SS pin to GND. The
second soft-start ramp time TD2 and TD4 can be calculated
based on the following equations:
TD2
=
1----.--1---x----R----_S----S--
6.25 x 25
(μs)
(EQ. 15)
TD4
=
(_{---V----V----I--D-----}–_{-----1---.--1----})_{--x---R-----S----S-- ( μ s )}
6.25 x 25
(EQ. 16)
For example, when VID is set to 1.5V and the R_SS is set at
100kΩ, the first soft-start ramp time TD2 will be 704µs and
the second soft-start ramp time TD4 will be 256µs.
After the DAC voltage reaches the final VID setting,
VR_RDY will be set to high with the fixed delay TD5. The
typical value for TD5 is 85µs.
VOUT, 500mV/DIV
TD1
TD2 TD3 TD4 TD5
EN_VTT
VR_RDY
500µs/DIV
FIGURE 8. SOFT-START WAVEFORMS
Current Sense Output
The current flowing out of the IOUT pin is equal to the
sensed average current inside ISL6326B. In typical
application, a resistor is placed from the IOUT pin to GND to
generate a voltage, which is proportional to the load current
and the resistor value:
V_IOUT
=
--R----^I--^O-----^U----^T-
N
------R----^X-------
R_ISEN
I_L
O
A
D
(EQ. 17)
where V_IOUT is the voltage at the IOUT pin, R_IOUT is the
resistor between the IOUT pin and GND, I_LOAD is the total
output current of the converter, R_ISEN is the sense resistor
connected to the ISEN+ pin, N is the active channel number,
and R_X is the DC resistance of the current sense element,
either the DCR of the inductor or R_SENSE depending on the
sensing method.
The resistor from the IOUT pin to GND should be chosen to
ensure that the voltage at the IOUT pin is less than 2V under
the maximum load current. If the IOUT pin voltage is higher
than 2V, overcurrent shutdown will be triggered, as
described in the Overcurrent Protection section.
A small capacitor can be placed between the IOUT pin and
GND to reduce the noise impact. If this pin is not used, tie it
to GND.
Fault Monitoring and Protection
The ISL6326B actively monitors output voltage and current
to detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 9 outlines
the interaction between the fault monitors and the VR_RDY
signal.
VR_RDY Signal
The VR_RDY pin is an open-drain logic output to indicate
that the soft-start period has completed and the output
voltage is within the regulated range. VR_RDY is pulled low
during shutdown and releases high after a successful soft-
start and a fixed delay TD5. VR_RDY will be pulled low when
an undervoltage or overvoltage condition is detected, or the
controller is disabled by a reset from EN_PWR, EN_VTT,
POR, or VID OFF-code.
Undervoltage Detection
The undervoltage threshold is set at 50% of the VID code.
When the output voltage at VSEN is below the undervoltage
threshold, VR_RDY is pulled low.
Overvoltage Protection
Regardless of the VR being enabled or not, the ISL6326B
overvoltage protection (OVP) circuit will be active after its
POR. The OVP thresholds are different under different
operation conditions. When VR is not enabled and during
the soft-start intervals TD1, TD2 and TD3, the OVP
threshold is 1.275V. Once the controller detects valid VID
input, the OVP trip point will be changed to DAC plus
175mV.
Two actions are taken by the ISL6326B to protect the
microprocessor load when an overvoltage condition occurs.
At the inception of an overvoltage event, all PWM outputs
are commanded low instantly (less than 20ns). This causes
the Intersil drivers to turn on the lower MOSFETs and pull
the output voltage below a level to avoid damaging the load.
When the VDIFF voltage falls below the DAC plus 75mV,
PWM signals enter a high-impedance state. The Intersil
drivers respond to the high-impedance input by turning off
both upper and lower MOSFETs. If the overvoltage condition
reoccurs, the ISL6326B will again command the lower
20
FN9286.0
April 21, 2006