ISL12029_10 Datasheet, PDF (29/30 Pages) Intersil Corporation – Real Time Clock/Calendar with I2C Bus™ and EEPROM

ISL12029, ISL12029A
Package Outline Drawing
M14.15
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 10/09
4
8.65
0.10 C A-B 2X
A3 ₆
14
8
D
DETAIL"A"
3.9
4
0.10 C D 2X
PIN NO.1
ID MARK
5
7
0.31-0.51
0.25M C A-B D
B3 6
TOP VIEW
6.0
0.20 C 2X
(0.35) x 45°
0.22±0.03
4° ± 4°
1.75 MAX
1.27
0.10-0.25
SIDE VIEW
1.25 MIN
0.10 C
H
DETAIL "A"
0.25
GAUGE PLANE _C
SEATING PLANE
0.10 C
(1.27)
(0.6)
(5.40)
(1.50)
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Datums A and B to be determined at Datum H.
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5. The pin #1 indentifier may be either a mold or mark feature.
6. Does not include dambar protrusion. Allowable dambar protrusion
shall be 0.10mm total in excess of lead width at maximum condition.
7. Reference to JEDEC MS-012-AB.
TYPICAL RECOMMENDED LAND PATTERN
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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29
FN6206.9
August 12, 2010