ISL12029_10 Datasheet, PDF (17/30 Pages) Intersil Corporation – Real Time Clock/Calendar with I2C Bus™ and EEPROM

ISL12029, ISL12029A
V_DD
V_BAT
V_TRIP
V_TRIP
BATTERY BACKUP
MODE
3.0V
2.2V
V_TRIP + V_TRIPHYS
FIGURE 14. BATTERY SWITCHOVER WHEN V_BAT > V_TRIP
OPTION 2 - LEGACY POWER CONTROL MODE
(DEFAULT FOR ISL12029)
The Legacy Mode follows conditions set in X1226 products.
In this mode, switching from V_DD to V_BAT is simply done by
comparing the voltages and the device operates from
whichever is the higher voltage. Care should be taken when
changing from Normal to Legacy Mode. If the V_BAT voltage is
higher than V_DD, then the device will enter battery backup and
unless the battery is disconnected or the voltage decreases,
the device will no longer operate from V_DD. If that is the
situation on initial power-up, then I²C communication may not
be possible. For these applications, the ISL12029A should be
used.
To select the Option 2, BSW bit in the Power Register must
be set to “BSW = 1.”
• Normal Mode (V_DD) to Battery Backup Mode (V_BAT)
To transition from the V_DD to V_BAT mode, the following
conditions must be met:
V_DD < V_BAT - V_BATHYS
• Battery Backup Mode (V_BAT) to Normal Mode (V_DD)
The device will switch from the V_BAT to V_DD mode when the
following condition occurs:
V_DD > V_BAT +V_BATHYS
The Legacy Mode power control conditions are illustrated in
Figure 15.
V_BAT
V_DD
OFF
VOLTAGE
ON
IN
FIGURE 15. BATTERY SWITCHOVER IN LEGACY MODE
Power-on Reset
Application of power to the ISL12029 activates a Power-on
Reset Circuit that pulls the RESET pin active. This signal
provides several benefits.
- It prevents the system microprocessor from starting to
operate with insufficient voltage.
- It prevents the processor from operating prior to
stabilization of the oscillator.
- It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
- It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
When V_DD exceeds the device V_RESET threshold value for
typically 250ms the circuit releases RESET, allowing the
system to begin operation. Recommended slew rate is
between 0.2V/ms and 50V/ms.
NOTE: If the V_BAT voltage drops below the data sheet
minimum of 1.8V and the V_DD power cycles to 0V then back
to V_DD voltage, then the RESET output may stay low and the
I²C communications will not operate. The V_BAT and V_DD
power will need to be cycled to 0V together to allow normal
operation again.
Watchdog Timer Operation
The Watchdog timer time-out period is selectable. By writing
a value to WD1 and WD0, the Watchdog timer can be set to
3 different time-out periods or off. When the Watchdog timer
is set to off, the Watchdog circuit is configured for low power
operation (see Table 8).
TABLE 8. WATCHDOG TIMER OPERATION
WD1
WD0
DURATION
1
1
disabled
1
0
250ms
0
1
750ms
0
0
1.75s
Watchdog Timer Restart
The Watchdog Timer is started by a falling edge of SDA
when the SCL line is high (START condition). The start
signal restarts the Watchdog timer counter, resetting the
period of the counter back to the maximum. If another
START fails to be detected prior to the Watchdog timer
expiration, then the RESET pin becomes active for one reset
time out period. In the event that the start signal occurs
during a reset time out period, the start will have no effect.
When using a single START to refresh Watchdog timer, a
STOP condition should be followed to reset the device back
to stand-by mode (see Figure 3).
In battery mode, the Watchdog timer function is disabled.
17
FN6206.9
August 12, 2010