ISL12029_10 Datasheet, PDF (18/30 Pages) Intersil Corporation – Real Time Clock/Calendar with I2C Bus™ and EEPROM

ISL12029, ISL12029A
Low Voltage Reset (LVR) Operation
When a power failure occurs, a voltage comparator
compares the level of the V_DD line versus a preset threshold
voltage (V_RESET), then generates a RESET pulse if it is
below V_RESET. The reset pulse will time-out 250ms after the
V_DD line rises above V_RESET. If the V_DD remains below
V_RESET, then the RESET output will remain asserted low.
Power-up and power-down waveforms are shown in
Figure 4. The LVR circuit is to be designed so the RESET
signal is valid down to V_DD = 1.0V.
When the LVR signal is active, unless the part has been
switched into the battery mode, the completion of an
in-progress non-volatile write cycle is unaffected, allowing a
non-volatile write to continue as long as possible (down to
the Reset Valid Voltage). The LVR signal, when active, will
terminate any in-progress communications to the device and
prevents new commands from disrupting any current write
operations. See “I²C Communications During Battery
Backup and LVR Operation” on page 25.
In battery mode, the RESET signal output is asserted LOW
when the V_DD voltage supply has dipped below the V_RESET
threshold. The RESET signal output will not return HIGH
until the device is back to V_DD mode even the V_DD voltage is
above V_RESET threshold.
Serial Communication
The device supports the I²C bidirectional serial bus protocol.
CLOCK AND DATA
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions (see Figure 16).
SCL
START CONDITION
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met (see Figure 17).
STOP CONDITION
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the Standby power mode after a read sequence. A stop
condition can only be issued after the transmitting device
has released the bus (see Figure 17).
ACKNOWLEDGE
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting 8-bits.
During the ninth clock cycle, the receiver will pull the SDA
line LOW to acknowledge that it received the 8-bits of data
(refer to Figure 18).
The device will respond with an acknowledge after recognition
of a start condition and if the correct Device Identifier and Select
bits are contained in the Slave Address Byte. If a write
operation is selected, the device will respond with an
acknowledge after the receipt of each subsequent 8-bit word.
The device will not acknowledge if the slave address byte is
incorrect.
SDA
DATA STABLE DATA CHANGE
DATA STABLE
FIGURE 16. VALID DATA CHANGES ON THE SDA BUS
SCL
SDA
START
STOP
FIGURE 17. VALID START AND STOP CONDITIONS
18
FN6206.9
August 12, 2010