ISL3873 Datasheet, PDF (25/31 Pages) Intersil Corporation – Wireless LAN Integrated Medium Access Controller with Baseband Processor

ISL3873
TX
POWER
RAMP
2
56 SYMBOL SYNC
20 SYMBOLS
AGC SETTLE AND LOCK
AND INITIAL DETECTION
20 SYMBOLS
7 SYM
VERIFY AND CIR/FREQUENCY
ESTIMATION AND CMF/NCO
JAMMING
SEED
DESCRAMBLER
START SFD SEARCH
FIGURE 16. ACQUISITION TIMELINE, NON DIVERSITY
SFD
16 SYMBOLS
SFD DET
START DATA
I_REF
V_REF
TX_AGC_IN
TX_IF_AGC
ANTSEL
ANTSEL
V_DDA (ANALOG)
GND (ANALOG)
V_DD (DIGITAL)
GND (DIGITAL)
6-BIT
ADC
6-BIT
DAC
TX AGC
CONTROL
REGISTER
TIMING
GENERATOR
MCLK
DAC
TXI+/-
TRANSMIT
FILTER
PREAMBLE/HEADER
CRC-16
GENERATOR
MODULATOR,
BARKER/CCK
TX_DATA
SCRAMBLER
TX
STATE
CONTROL
DAC
INTERNAL
SIGNALS
TXQ+/-
TX_RDY
TXCLK
TXD
RXCLK
CCA
MAC
CONTROL
SIGNALS
TX_PE
MCLK
FIGURE 17. DSSS BASEBAND PROCESSOR, TRANSMIT SECTION
Meanwhile signal quality and signal frequency
measurements are made simultaneous with symbol timing
measurements. A CS1 followed by SQ1 active, or two
consecutive SQ1s will cause the part to finish the acquisition
phase and enter the tracking phase.
Prior to initial acquisition the NCO is inactive (0Hz) and
carrier phase measurement are done on a symbol by symbol
basis. After acquisition, coherent DPSK demodulation is in
effect. After a brief setup time as illustrated on the timeline,
the signal begins to emerge from the demodulator.
It takes 7 more symbols to seed the descrambler before valid
data is available. This occurs in time for the SFD to be received.
At this time the demodulator is tracking and in the coherent
PSK demodulation mode so it will no longer acquire new
signals. If a much larger signal overrides the signal being
demodulated (a collision), the demodulator will abort the
tracking process and attempt to acquire the new signal. Failure
to find an SFD within the SFD timeout interval will result in a
receiver reset and return to acquisition mode.
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