ISL3873 Datasheet, PDF (18/31 Pages) Intersil Corporation – Wireless LAN Integrated Medium Access Controller with Baseband Processor

ISL3873
Baseband Processor
The Baseband Processor operation is controlled by the
ISL3873 firmware. Detailed information on programming the
Baseband Processor can be obtain by contacting the factory.
BBP Packet Reception
The receive demodulator scrutinizes I and Q for packet
activity. When a packet arrives at a valid signal level the
demodulator acquires and tracks the incoming signal. It then
sifts through the demodulator data for the Start Frame
Delimiter (SFD). After SFD is detected, The BBP picks off
the needed header fields from the real-time demodulated
bitstream.
Assuming all is well with the header, the BBP decodes the
signal field in the header and switches to the appropriate
data rate. If the signal field is not recognized, or the CRC16
is in error, the demodulator will return to acquisition mode
looking for another packet. If all is well with the header, and
after the demodulator has switched to the appropriate data
rate, then the demodulator will continue to provide data to
the MAC in the ISL3873 indefinitely.
RX I/Q A/D Interface
The PRISM baseband processor chip (ISL3873) includes
two 6-bit Analog to Digital converters (A/Ds) that sample the
balanced differential analog input from the IF down converter
device (HFA3783). The I/Q A/D clock, samples at twice the
chip rate with a nominal sampling rate of 22MHz.
The interface specifications for the I and Q A/Ds are listed in
Table 5. The ISL3873 is designed to be DC coupled to the
HFA3783.
TABLE 5. I, Q, A/D SPECIFICATIONS
PARAMETER
MIN
TYP
MAX
Full Scale Input Voltage (V_P-P)
Input Bandwidth (-0.5dB)
0.90
1.00
1.10
-
11MHz
-
Input Capacitance (pF)
-
2
-
Input Impedance (DC)
5kΩ
-
-
f_S (Sampling Frequency)
-
22MHz
-
The voltages applied to pin 16, V_REF and pin 21, I_REF set
the references for the internal I and Q A/D converters. In
addition, For a nominal I/Q input of 400mV_P-P, the
suggested V_REF voltage is 1.2V.
AGC Circuit
The AGC circuit as shown in Figure 12 is designed to adjust
for signal level variations and optimize A/D performance for
the I and Q inputs by maintaining the proper headroom on
the 6-bit converters. There are two gain stages being
controlled. At RF, the gain control is a 30dB step change.
This RF gain control optimizes the receiver dynamic range
when the signal level is high and maintains the noise figure
of the receiver when it is needed most at low signal level. At
IF, the gain control is linear and covers the bulk of the gain
control range of the receiver.
The AGC loop is partially digital which allows for holding the
gain fixed during a packet. The AGC sensing mechanism uses
a combination of the I and Q A/D converters and the detected
signal level in the IF to determine the gain settings. The A/D
outputs are monitored in the ISL3873 for the desired nominal
level. When it is reached, by adjusting the receiver gain, the
gain control is locked for the remainder of the packet.
RX_AGC_IN Interface
The signal level in the IF stage is monitored to determine
when to impose the 30dB gain reduction in the RF stage.
This maximizes the dynamic range of the receiver by
keeping the RF stages out of saturation at high signal levels.
When the IF circuits’ sensor output reaches 0.5V_DD, the
ISL3873 comparator switches in the 30dB pad and also
adds 30dB of gain to the IF AGC amplifier. This
compensates the IF AGC and RSSI measures.
TX I/Q DAC Interface
The transmit section outputs balanced differential analog
signals from the transmit DACs to the HFA3783. These are
DC coupled and digitally filtered.
Transmitter Description
The ISL3873 transmitter is designed as a Direct Sequence
Spread Spectrum Phase Shift Keying (DSSS PSK)
modulator which is capable of handling data rates of up to
11Mbps (refer to AC and DC specifications). The various
modes of the modulator are Differential Binary Phase Shift
Keying (DBPSK) for 1Mbps, Differential Quaternary Phase
Shift Keying (DQPSK) for 2Mbps, and Complementary Code
Keying (CCK) for 5.5Mbps and 11Mbps.
CCK is essentially a quadra-phase form of M-ARY Orthogonal
Keying. A description of that modulation can be found in
Chapter 5 of: “Telecommunications System Engineering”, by
Lindsey and Simon, Prentiss Hall publishing.
The implemented data rates using a clock rate of 44MHz are
shown in Table 6 and the modulation schemes are indicated
in Figure 13. The major functional blocks of the transmitter
include a Processor Interface, Modulator, Data Scrambler,
Preamble/Header Generator, TX Filter, AGC Control, and
ADC and DAC circuits. Figure 17 provides a basic block
diagram of the DSSS Baseband Processor with an
emphasis on the transmitter section. Figure 19 provides a
basic block diagram of the DSSS Baseband Processor with
an emphasis on the receive section.
The preamble is always transmitted as the DBPSK waveform
while the header can be configured to be either DBPSK, or
DQPSK, and data packets can be configured for DBPSK,
DQPSK, or CCK. The preamble is used by the receiver to
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