|
ISL3873 Datasheet, PDF (20/31 Pages) Intersil Corporation – Wireless LAN Integrated Medium Access Controller with Baseband Processor | |||
|
◁ |
ISL3873
DATA
802.11 DSSS BPSK
1Mbps
BARKER
IOUT
QOUT
CHIP
RATE
SYMBOL
RATE
1 BIT ENCODED TO
ONE OF 2 CODE
WORDS
(TRUE-INVERSE)
11 CHIPS
11 MC/S
1 MS/S
802.11 DSSS QPSK
2Mbps
BARKER
2 BITS ENCODED
TO ONE OF
4 CODE WORDS
11 CHIPS
11 MC/S
1 MS/S
5.5Mbps CCK
COMPLEX
SPREAD FUNCTIONS
11Mbps CCK
COMPLEX
SPREAD FUNCTIONS
4 BITS ENCODED
TO ONE OF 16
COMPLEX CCK
CODE WORDS
8 BITS ENCODED
TO ONE OF 256
COMPLEX CCK
CODE WORDS
8 CHIPS
11 MC/S
1.375 MS/S
8 CHIPS
11 MC/S
1.375 MS/S
I vs. Q
FIGURE 13. MODULATION MODES
PREAMBLE (SYNC) Start FRAME DELIMITER SIGNAL FIELD SERVICE FIELD
128/56 BITS
16 BITS
8 BITS
8 BITS
LENGTH FIELD CRC16
16 BITS
16 BITS
PREAMBLE
HEADER
FIGURE 14. 802.11 PREAMBLE/HEADER
Header Field
The header ï¬eld is deï¬ned by four ï¬elds which are shown in
Figure 14. These ï¬elds are Signal Field, Service Field,
Length Field and CITT-CRC16 Field. They are further
deï¬ned by the following:
Signal Field (8 Bits) - This ï¬eld indicates what data rate the
data packet that follows the header will be. The ISL3873
receiver looks at the signal ï¬eld to determine whether it
needs to switch from DBPSK demodulation into DQPSK, or
CCK demodulation at the end of the preamble and header
ï¬elds.
Service Field (8 Bits) - The MSB of this ï¬eld is used to
indicate the correct length when the length ï¬eld value is
ambiguous at 11Mbps. See IEEE STD 802.11 for deï¬nition
of the other bits. Bit 2 is used by the ISL3873 to indicate that
the carrier reference and the bit timing references are
derived from the same oscillator (locked oscillators).
Length Field (16 Bits) - This ï¬eld indicates the number of
microseconds it will take to transmit the payload data
(PSDU). The external controller (MAC) will check the length
ï¬eld in determining when it needs to de-assert RX_PE.
CCITT - CRC 16 Field (16 Bits) - This ï¬eld includes the
16-bit CCITT - CRC 16 calculation of the three header ï¬elds.
This value is compared with the CCITT - CRC 16 code
calculated at the receiver. The ISL3873 receiver will indicate
a CCITT - CRC 16 error via CR24 bit 2 and will lower
MD_RDY and reset the receiver to the acquisition mode if
there is an error.
The CRC or cyclic Redundancy Check is a CCITT CRC-16
FCS (Frame Check Sequence). It is the ones complement of
the remainder generated by the modulo 2 division of the
protected bits by the polynomial:
x16 + x12 + x5 + 1
The protected bits are processed in transmit order. All CRC
calculations are made ahead of data scrambling. A shift
register with two taps is used for the calculation. It is preset
to all ones and then the protected ï¬elds are shifted through
the register. The output is then complemented and the
residual shifted out MSB ï¬rst.
The following Conï¬guration Registers (CR) are used to
program the preamble/header functions, more programming
details about these registers can be found in the Control
Registers section of this document:
20
|
▷ |