ISL3873 Datasheet, PDF(12/31 Page) Intersil Corporation – Wireless LAN Integrated Medium Access Controller with Baseband Processor

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ISL3873 Datasheet, PDF (12/31 Pages) Intersil Corporation – Wireless LAN Integrated Medium Access Controller with Baseband Processor

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ISL3873

LARGE SERIAL EEPROM

MISO (PJ2)

ISL3873

SD (PJ1)

SCLK (PJ0)

CS# (TCLKIN)

PULLUP

SCK

PULLUP

RESET#

WP#

45DB011

SMALL SERIAL EEPROM

PULLUP

ISL3873 CS# (TCLKIN)

SCLK (PJ0)

SDA

SCL

24C08 (NOTE)

NOTE: Must operate at 400kHz AT 3.3VDC

FIGURE 8. SERIAL EEPROM INTERFACE

External Memory Interface

The ISL3873 provides separate external chip selects for

code space and data storage space. Code space is

accessible as data space through an overlay mechanism,

except for an internal ROM. Refer to Figures 6, 7 and 8 for

ISL3873 memory conï¬guration detail examples.

The maximum possible memory space size is 4Mbytes. If

USB is the host interface, this is reduced to 1Mbyte.

Most of the data store space is reserved for storage of

received and transmitted data, with some areas reserved for

use by ï¬rmware. However, a portion of the data store may be

allocated as code store. This permits higher speed

instruction execution, by using fast RAMs, than is possible

from Flash memories. The maximum size of this overlay is

the full code space address range, 128Kbytes, and is

allocated in independent sections of 16KBytes each, on

16Kbyte boundaries, ranging from the highest address of the

actual physical memory space and extending down.

Mapping code execution to RAM requires the RAM to have

code written into it. Typically, this is done by placing code in a

non-volatile memory such as a Flash in the code space. At

initialization, the code in the non-volatile memory transfers itself

to RAM, maps the appropriate blocks of the code space to the

RAM, and then branches to begin execution from RAM. This

allows low cost, slow Flash devices to hold an entire code

image, which can be executed much faster from RAM. If code

is not placed in an external non-volatile memory as described

here, it must be transferred to the RAM via the Host Interface.

Slow memories are not dynamically sensed. Following reset,

the instruction clock operates with a slower cycle while the

Flash is copied to RAM. Once code has been copied from

Flash to RAM, execution transfers to RAM and the clock is

raised to the normal operating frequency.

As mentioned above, it is feasible to operate without a code

image in a non-volatile memory. In such a system, the

ï¬rmware must be downloaded to RAM through the host

interface before operation can commence.

The external SRAM memory must be organized in a 16-bit

width to provide adequate performance to implement the

802.11 protocol at 11Mb/s rates. Systems designed for lower

performance applications may be able to use 8-bit wide

memory.

The minimum external memory is 128Kbytes of SRAM,

organized 8 or 16 bits wide. Typical applications, including

802.11 station designs, use 256Kbytes organized 128K x 16.

An access point application could make use of the full address

space of the device with 4Mbytes organized a 2M x 16.

The ISL3873 supports 8 or 16-bit code space, and 8 or 16-bit

data space. Code space is typically populated with the lease

expensive Flash memory available, usually an 8-bit device.

Data space is usually populated with high-speed RAMs

configured as a 16-bit space. This mixing of 8/16 bit spaces is

fully supported, and may be done in any combination desired

for code and data space.

The ISL3873 supports direct control of single chip 16-bit

wide SRAMs with high/low byte enables, as well as direct

control of a 16-bit space constructed from 8-bit wide SRAMs.

The type of memory conï¬guration is speciï¬ed via the

appropriate MD pin, sensed when the ISL3873 is reset.

ISL3873 pin MUBE-/MA0/MWEH- functions as Address 0 for

8-bit access, (such as Flash) as MWEH (High Byte Write

Enable) when two x8 memories are conï¬gured as a single

x16 space, and as the upper Byte Enable when a single x16

memory is used. No external logic is required to generate

the required signals for both types of memory conï¬gurations,

even when both exist together; all that is required is for the

ISL3873 code to conï¬gure the ISL3873 memory controller to

generate the proper signals for the particular address space

being accessed.

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