ISL3873 Datasheet, PDF (21/31 Pages) Intersil Corporation – Wireless LAN Integrated Medium Access Controller with Baseband Processor

ISL3873
CR 3 - Defines the short preamble length minus the SFD in
symbols. The 802.11 protocol requires a setting of 56d = 38h
for the optional short preamble.
CR 4 - Defines the long preamble length minus the SFD in
symbols. The 802.11 protocol requires a setting of
128d = 80h for the mandatory long preamble.
CR 5 Bits 0, 1 - These bits of the register set the Signal field
to indicate what modulation is to be used for the data portion
of the packet.
CR 6 - The value to be used in the Service field.
CR 7 and 8 - Defines the value of the transmit data length
field. This value includes all symbols following the last
header field symbol and is in microseconds required to
transmit the data at the chosen data rate.
The packet consists of the preamble, header and MAC Protocol
Data Unit (MPDU). The data is transmitted exactly as received
from the control processor. Some dummy bits will be appended
to the end of the packet to ensure an orderly shutdown of the
transmitter. This prevents spectrum splatter. At the end of a
packet, the external controller is expected to de-assert the
TX_PE line to shut the transmitter down.
Scrambler and Data Encoder Description
The modulator has a data scrambler that implements the
scrambling algorithm specified in the IEEE 802.11 standard.
This scrambler is used for the preamble, header, and data in
all modes. The data scrambler is a self synchronizing circuit.
It consists of a 7-bit shift register with feedback from
specified taps of the register. Both transmitter and receiver
use the same scrambling algorithm. The scrambler can be
disabled by setting CR32 bit 2 to 1.
NOTE: Be advised that the IEEE 802.11 compliant scrambler in the
ISL3873 has the property that it can lock up (stop scrambling) on
random data followed by repetitive bit patterns. The probability of this
happening is 1/128. The patterns that have been identified are all
zeros, all ones, repeated 10s, repeated 1100s, and repeated
111000s. Any break in the repetitive pattern will restart the scrambler.
To ensure that this does not cause any problem, the CCK waveform
uses a ping pong differential coding scheme that breaks up repetitive
0’s patterns.
Scrambling is done by division with a prescribed polynomial
as shown in Figure 15. A shift register holds the last quotient
and the output is the exclusive or of the data and the sum of
taps in the shift register. The transmit scrambler seed for the
long preamble or for the short preamble can be set with
CR48 or CR49.
SERIAL DATA
IN
XOR
Z^-1 Z^-2 Z^-3 Z^-4
XOR
SERIAL
DATA OUT
Z^-5 Z^-6 Z^-7
FIGURE 15. SCRAMBLING PROCESS
For the 1Mbps DBPSK data rates and for the header in all rates
using the long preamble, the data coder implements the
desired DBPSK coding by differential encoding the serial data
from the scrambler and driving both the I and Q output
channels together. For the 2Mbps DQPSK data rate and for the
header in the short preamble mode, the data coder implements
the desired coding as shown in the DQPSK Data Encoder
Table 7. This coding scheme results from differential coding of
dibits (2 bits). Vector rotation is counterclockwise although bits
6 and 7 of configuration register CR 1 can be used to reverse
the rotation sense of the TX or RX signal if desired.
Spread Spectrum Modulator Description
The modulator is designed to generate DBPSK, DQPSK, and
CCK spread spectrum signals. The modulator is capable of
automatically switching its rate where the preamble is
DBPSK modulated, and the data and/or header are
modulated differently. The modulator can support date rates
of 1, 2, 5.5 and 11Mbps. Quadraphase (I/Q) modulation is
used at the baseband for all modulation modes. Further
information on the programming details required to set up
the modulator can be obtained by contacting the factory.
TABLE 7. DQPSK DATA ENCODER
PHASE SHIFT
0
+90
+180
-90
DIBIT PATTERN (d0, d1)
d0 IS FIRST IN TIME
00
01
11
10
In the 1Mbps DBPSK mode, the I and Q Channels are
connected together and driven with the output of the scrambler
and differential encoder. The I and Q Channels are then both
multiplied with the 11-bit Barker word at the spread rate. The I
and Q signals go to the Quadrature upconverter (HFA3724) to
be modulated onto a carrier. Thus, the spreading and data
modulation are BPSK modulated onto the carrier.
For the 2Mbps DQPSK mode, the serial data is formed into
dibits or bit pairs in the differential encoder as detailed
above. One of the bits from the differential encoder goes to
the I Channel and the other to the Q Channel. The I and Q
Channels are then both multiplied with the 11-bit Barker
word at the spread rate. This forms QPSK modulation at the
symbol rate with BPSK modulation at the spread rate.
CCK Modulation
For the CCK modes, the spreading code length is 8 complex
chips and based on complementary codes. The chipping rate is
11Mchip/s. The following formula is used to derive the CCK
code words that are used for spreading both 5.5 and 11Mbps:
c
=
 ^{e j ( ϕ1}
+
ϕ₂
+
ϕ₃
+
ϕ₄)_,
e^j(ϕ1
+
ϕ₃
+
ϕ₄)_,
j
e
(ϕ₁
+
ϕ₂
+
ϕ₄
)
,

–e^j(ϕ1
+
ϕ₄
)
,
j
e
(
ϕ₁
+
ϕ₂
+
ϕ₃
)
,
e
j
(
ϕ₁
+
ϕ₃)_,
–e
j
(
ϕ₁
+
ϕ₂)_,
e^jϕ1



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