ISL12022M Datasheet, PDF (25/27 Pages) Intersil Corporation – Real Time Clock with Embedded Crystal, ±5ppm Accuracy

ISL12022M
The diode, D_BAT will add a small drop to the battery voltage
but will protect the circuit should battery voltage drop below
1.8V. The jumper is added as a safeguard should the battery
ever need to be disconnected from the circuit.
The V_DD negative slew rate should be limited to below the
data sheet spec (10V/ms) otherwise battery switchover can
be delayed, resulting in SRAM contents corruption and
oscillator operation interruption.
Layout Considerations
The ISL12022M contains a quarts crystal and requires special
handling during PC board assembly. Excessive shock and
vibrations should be avoided, especially with automated
handling equipment. Ultrasound cleaning is not advisable as it
subjects the crystal to resonance and possible failure. See also
Note 2 on page 3 in the specifications tables, which pertains to
solder reflow effects on oscillator accuracy.
The part of the package that has NC pins from pin 1 to 5 and
from pin 16 to 20 contains the crystal. Low frequency RTC
crystals are known to pick up noise very easily if layout
precautions are not followed, even embedded within a plastic
package. Most instances of erratic clocking or large accuracy
errors can be traced to the susceptibility of the oscillator circuit
to interference from adjacent high speed clock or data lines.
Careful layout of the RTC circuit will avoid noise pickup and
insure accurate clocking.
Figure 21 shows a suggested layout for the ISL12022M
device. The following main precautions should be followed:
• Do not run the serial bus lines or any high speed logic lines
in the vicinity of pins 1 and 20, or under the package. These
logic level lines can induce noise in the oscillator circuit,
causing misclocking.
• Add a ground trace around the device with one end
terminated at the chip ground. This guard ring will provide
termination for emitted noise in the vicinity of the RTC device.
GROUND
RING
F_OUT
SCL
SDA
FIGURE 21. SUGGESTED LAYOUT FOR THE ISL12022M
• Be sure to ground pins 6 and 15 as well as pin 8 as these
all insure the integrity of the device ground
• Add a 0.1µF decoupling capacitor at the device V_DD pin,
especially when using the 32.768kHz F_OUT function.
The best way to run clock lines around the RTC is to stay
outside of the ground ring by at least a few millimeters. Also,
use the V_BAT and V_DD as guard ring lines as well, they can
isolate clock lines from the oscillator section. In addition, if
the IRQ/F_OUT pin is used as a clock, it should be routed
away from the RTC device as well.
Measuring Oscillator Accuracy
The best way to analyze the ISL12022M frequency accuracy
is to set the IRQ/F_OUT pin for a specific frequency, and look
at the output of that pin on a high accuracy frequency
counter (at least 7 digits accuracy). Note that the IRQ/F_OUT
is an drain output and will require a pull-up resistor.
Using the 1.0Hz output frequency is the most convenient as
the ppm error is expressed in Equation 6:
ppm error = F_OUT – 1 • 1e6
(EQ. 6)
Other frequencies may be used for measurement but the
error calculation becomes more complex. Use the F_OUT
output and a frequency counter for the most accurate
results. Also, when the proper layout guidelines above are
observed, the oscillator should start-up in most circuits in
less than one second.
Temperature Compensation Operation
The ISL12022M temperature compensation feature needs to
be enabled by the user. This must be done in a specific order
as follows.
1. Read register 0Dh, the BETA register. This register
contains the 5-bit BETA trimmed value, which is
automatically loaded on initial power-up. Mask off the 5
LSB’s of the value just read.
2. Bit 7 of the BETA register is the master enable control for
temperature sense operation. Set this to “1” to allow
continuous temperature frequency correction. Frequency
correction will then happen every 60 seconds with V_DD
applied.
3. Bits 5 and 6 of the BETA register control temperature
compensation in battery backup mode (see Table 15).
Set the values for the operation desired.
4. Write back to register 0Dh making sure not to change the
5 LSB values, and include the desired compensation
control bits.
Note that every time the BETA register is written with the
TSE bit = 1, a temperature compensation cycle is instigated
and a new correction value will be loaded into the
FATR/FDTR registers (if the temperature changed since the
last conversion).
Also note that registers 0Bh and 0Ch, the ITR0 and ALPHA
registers, are READ-ONLY, and cannot be written to. Also
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FN6668.4
December 18, 2008