ISL12022M Datasheet, PDF (15/27 Pages) Intersil Corporation – Real Time Clock with Embedded Crystal, ±5ppm Accuracy

ISL12022M
Power Supply Control Register (PWR_VDD)
CLEAR TIME STAMP BIT (CLRTS)
ADDR 7 6 5 4 3
2
1
0
09h CLRTS 0 0 0 0 V_DDTrip2 V_DDTrip1 V_DDTrip0
This bit clears Time Stamp V_DD to Battery (TSV2B) and Time
Stamp Battery to V_DD Registers (TSB2V). The default setting
is 0 (CLRTS = 0) and the Enabled setting is 1 (CLRTS = 1).
V_DD BROWNOUT TRIP VOLTAGE BITS (V_DDTRIP<2:0>)
These bits set the trip level for the V_DD alarm, indicating that
V_DD has dropped below a preset level. In this event, the
LVDD bit in the Status Register is set to “1”. See Table 6.
V_DDTrip2
0
0
0
0
1
1
TABLE 6. V_DD TRIP LEVELS
V_DDTrip1
0
0
1
1
0
0
V_DDTrip0
0
1
0
1
0
1
TRIP
VOLTAGE
(V)
2.295
2.550
2.805
3.060
4.250
4.675
Battery Voltage Trip Voltage Register (PWR_VBAT)
This register controls the trip points for the two V_BAT alarms,
with levels set to approximately 85% and 75% of the nominal
battery level.
TABLE 7.
ADDR 7 6
5
4
3
2
1
0
0Ah D RESEALB VB85Tp2 VB85Tp1 VB85Tp0 VB75Tp2 VB75Tp1 VB75Tp0
RESEAL BIT (RESEALB)
This is the Reseal bit for actively disconnecting the V_BAT pin
from the internal circuitry. Setting this bit allows the device to
disconnect the battery and eliminate standby current drain
while the device is unused. Once V_DD is powered up, this bit is
reset and the V_BAT pin is then connected to the internal
circuitry.
The application for this bit involves placing the chip on a
board with a battery and testing the board. Once the board is
tested and ready to ship, it is desirable to disconnect the
battery to keep it fresh until the board or unit is placed into
final use. Setting RESEALB = “1” initiates the battery
disconnect, and after V_DD power is cycled down and up
again, the RESEAL bit is cleared to “0”.
BATTERY LEVEL MONITOR TRIP BITS (VB85TP <2:0>)
Three bits select the first alarm (85% of Nominal V_BAT) level for
the battery voltage monitor. There are total of 7 levels that could
be selected for the first alarm. Any of the of levels could be
selected as the first alarm with no reference as to nominal
Battery voltage level. See Table 8.
VB85Tp2
0
0
0
0
1
1
1
TABLE 8. VB85T ALARM LEVEL
VB85Tp1
VB85Tp0
BATTERY ALARM
TRIP LEVEL
(V)
0
0
2.125
0
1
2.295
1
0
2.550
1
1
2.805
0
0
3.060
0
1
4.250
1
0
4.675
BATTERY LEVEL MONITOR TRIP BITS (VB75TP <2:0>)
Three bits select the second alarm (75% of Nominal V_BAT)
level for the battery voltage monitor. There are total of 7 levels
that could be selected for the second alarm. Any of the of levels
could be selected as the second alarm with no reference as to
nominal Battery voltage level. See Table 9.
TABLE 9. BATTERY LEVEL MONITOR TRIP BITS
(VB75TP <2:0>)
VB75Tp2
VB75Tp1
VB75Tp0
BATTERY ALARM
TRIP LEVEL
(V)
0
0
0
1.875
0
0
1
2.025
0
1
0
2.250
0
1
1
2.475
1
0
0
2.700
1
0
1
3.750
1
1
0
4.125
Initial AT and DT Setting Register (ITRO)
These bits are used to trim the initial error (at room
temperature) of the crystal. Both Digital Trimming (DT) and
Analog Trimming (AT) methods are available. The digital
trimming uses clock pulse skipping and insertion for
frequency adjustment. Analog trimming uses load
capacitance adjustment to pull the oscillator frequency. A
range of +62.5ppm to -61.5ppm is possible with combined
digital and analog trimming.
Initial values for the ITR0 register are preset internally and
recalled to RAM registers on power-up. These values are
pre-set in device production and are READ-ONLY. They
cannot be overwritten by the user. If an application
requires adjustment of the IATR bits outside the preset
values, the user should contact Intersil.
15
FN6668.4
December 18, 2008