ISL12022M Datasheet, PDF (24/27 Pages) Intersil Corporation – Real Time Clock with Embedded Crystal, ±5ppm Accuracy

ISL12022M
select bits with “1101111” or “1010111”. Upon a correct
compare, the device outputs an acknowledge on the SDA line.
Following the Slave Byte is a one byte word address. The word
address is either supplied by the master device or obtained
from an internal counter. On power-up, the internal address
counter is set to address 00h, so a current address read starts
at address 00h. When required, as part of a random read, the
master must supply the 1 Word Address Bytes, as shown in
Figure 20.
In a random read operation, the slave byte in the “dummy write”
portion must match the slave byte in the “read” section. For a
random read of the Control/Status Registers, the slave byte
must be “1101111x” in both places.
1
1
0
1
11
1
R/W
SLAVE
ADDRESS BYTE
A7 A6 A5 A4 A3 A2 A1 A0 WORD ADDRESS
D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE
FIGURE 18. SLAVE ADDRESS, WORD ADDRESS, AND DATA
BYTES
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL12022M responds with an ACK. At this time, the I²C
interface enters a standby state.
Read Operation
A Read operation consists of a three byte instruction, followed
by one or more Data Bytes (see Figure 20). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the ISL12022M responds with an ACK. Then the ISL12022M
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each
byte. The master terminates the read operation (issuing a
STOP condition) following the last bit of the last Data Byte
(see Figure 20).
The Data Bytes are from the memory location indicated by
an internal pointer. This pointer’s initial value is determined
by the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 13h, the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
Application Section
Battery Backup Details
The ISL12022M has automatic switchover to battery backup
when the V_DD drops below the V_BAT mode threshold. A wide
variety of backup sources can be used, including standard
and rechargeable lithium, supercapacitors, or regulated
secondary sources. The serial interface is disabled in battery
backup, while the oscillator and RTC registers are
operational. The SRAM register contents are powered to
preserve their contents as well.
The input voltage range for V_BAT is 1.8V to 5.5V, but keep in
mind the temperature compensation only operates for
V_BAT > 2.7V. Note that the device is not guaranteed to
operate with a V_BAT < 1.8V, so the battery should be
changed before discharging to that level. It is strongly
advised to monitor the low battery indicators in the status
registers and take action to replace discharged batteries.
If a supercapacitor is used, it is possible that it may discharge
to below 1.8V during prolonged power-down. Once powered
up, the device may lose serial bus communications until both
V_DD and V_BAT are powered down together. To avoid that
situation, including situations where a battery may discharge
deeply, the circuit in Figure 19 can be used.
V_DD = 2.7V
TO 5.5V
C_IN
0.1µF
ISL12022M
VDD VBAT
GND
J_BAT
C_BAT
0.1µF
D_BAT
BAT43W
+V^{BAT = 1.8V}
TO 3.2V
FIGURE 19. SUGGESTED BATTERY BACKUP CIRCUIT
SIGNALS ^S
S
FROM THE ^T IDENTIFICATION
T _{IDENTIFICATION}
MASTER ^A
BYTE WITH
ADDRESS
A _{BYTE WITH}
A
R
R/W = 0
BYTE
R
R/W = 1
C
T
T
K
SIGNAL AT
SDA
11011110
A
SIGNALS FROM
C
THE SLAVE
K
11011111
A
A
C
C _{FIRST READ}
K
K _{DATA BYTE}
FIGURE 20. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)
24
S
A
T
C
O
K
P
LAST READ
DATA BYTE
FN6668.4
December 18, 2008