ISL12022M Datasheet, PDF(14/27 Page) Intersil Corporation – Real Time Clock with Embedded Crystal, ±5ppm Accuracy

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ISL12022M Datasheet, PDF (14/27 Pages) Intersil Corporation – Real Time Clock with Embedded Crystal, ±5ppm Accuracy

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ISL12022M

LOW VDD INDICATOR BIT (LVDD)

This bit indicates when VDD has dropped below the

pre-selected trip level (Brownout Mode). The trip points for

brownout levels are selected by three bits: VDDTrip2,

VDDTrip1 and VDDTrip0 in PWR_VDD registers.

LOW BATTERY INDICATOR 85% BIT (LBAT85)

This bit indicates when the battery level has dropped below

the pre-selected trip levels (85% of battery voltage). The trip

points are selected by three bits: VB85Tp2, VB85Tp1 and

VB85Tp0 in the PWR_VBAT registers.

LOW BATTERY INDICATOR 75% BIT (LBAT75)

This bit indicates when the battery level has dropped below

the pre-selected trip levels (75% of battery voltage). The trip

points are selected by three bits: VB75Tp2, VB75Tp1 and

VB75Tp0 in the PWR_VBAT registers.

REAL TIME CLOCK FAIL BIT (RTCF)

This bit is set to a â1â after a total power failure. This is a read

only bit that is set by hardware (ISL12022M internally) when

the device powers up after having lost all power (defined as

VDD = 0V and VBAT = 0V). The bit is set regardless of

whether VDD or VBAT is applied first. The loss of only one of

the supplies does not set the RTCF bit to â1â. The first valid

write to the RTC section after a complete power failure

resets the RTCF bit to â0â (writing one byte is sufficient).

Interrupt Control Register (INT)

TABLE 3. INTERRUPT CONTROL REGISTER (INT)

ADDR 7

3210

08h ARST WRTC IM FOBATB FO3 FO2 FO1 FO0

AUTOMATIC RESET BIT (ARST)

This bit enables/disables the automatic reset of the ALM,

LVDD, LBAT85, and LBAT75 status bits only. When ARST

bit is set to â1â, these status bits are reset to â0â after a valid

read of the respective status register (with a valid STOP

condition). When the ARST is cleared to â0â, the user must

manually reset the ALM, LVDD, LBAT85, and LBAT75 bits.

WRITE RTC ENABLE BIT (WRTC)

The WRTC bit enables or disables write capability into the

RTC Timing Registers. The factory default setting of this bit

is â0â. Upon initialization or power-up, the WRTC must be set

to â1â to enable the RTC. Upon the completion of a valid

write (STOP), the RTC starts counting. The RTC internal

1Hz signal is synchronized to the STOP condition during a

valid write cycle.

INTERRUPT/ALARM MODE BIT (IM)

This bit enables/disables the interrupt mode of the alarm

function. When the IM bit is set to â1â, the alarm will operate

in the interrupt mode, where an active low pulse width of

250ms will appear at the IRQ/FOUT pin when the RTC is

triggered by the alarm, as defined by the alarm registers

(0Ch to 11h). When the IM bit is cleared to â0â, the alarm will

operate in standard mode, where the IRQ/FOUT pin will be

set low until the ALM status bit is cleared to â0â.

TABLE 4.

IM BIT

INTERRUPT/ALARM FREQUENCY

Single Time Event Set By Alarm

Repetitive/Recurring Time Event Set By Alarm

FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)

This bit enables/disables the IRQ/FOUT pin during battery

backup mode (i.e. VBAT power source active). When the

FOBATB is set to â1â, the IRQ/FOUT pin is disabled during

battery backup mode. This means that both the frequency

output and alarm output functions are disabled. When the

FOBATB is cleared to â0â, the IRQ/FOUT pin is enabled

during battery backup mode. Note that the open drain

IRQ/FOUT pin will need a pull-up to the battery voltage to

operate in battery backup mode.

FREQUENCY OUT CONTROL BITS (FO <3:0>)

These bits enable/disable the frequency output function and

select the output frequency at the IRQ/FOUT pin. See Table 5

for frequency selection. Default for the ISL12022M is

FO<3:0> = 1h, or 32.768kHz output (FOUT is ON). When the

frequency mode is enabled, it will override the alarm mode at

the IRQ/FOUT pin.

TABLE 5. FREQUENCY SELECTION OF IRQ/FOUT PIN

FREQUENCY,

FOUT

UNITS FO3

FO2 FO1 FO0

32768

4096

1024

1/2

1/4

1/8

1/16

1/32

FN6668.4

December 18, 2008

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