ISL12022M Datasheet, PDF (23/27 Pages) Intersil Corporation – Real Time Clock with Embedded Crystal, ±5ppm Accuracy

ISL12022M
SCL
SDA
START
DATA
DATA
DATA
STABLE CHANGE STABLE
STOP
FIGURE 15. VALID DATA CHANGES, START AND STOP CONDITIONS
SCL FROM
MASTER
1
SDA OUTPUT FROM
TRANSMITTER
8
9
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
HIGH IMPEDANCE
START
ACK
FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER
SIGNALS FROM
THE MASTER
WRITE
S
T
A ^{IDENTIFICATION}
R
BYTE
T
ADDRESS
BYTE
S
DATA
T
BYTE
O
P
SIGNAL AT SDA
11011110 0000
SIGNALS FROM
THE ISL12022M
A
A
A
C
C
C
K
K
K
FIGURE 17. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)
An acknowledge (ACK) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (see Figure 16).
The ISL12022M responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again, after successful receipt of an Address Byte. The
ISL12022M also responds with an ACK after receiving a
Data Byte of a write operation. The master must respond
with an ACK after receiving a Data Byte of a read operation.
Device Addressing
Following a start condition, the master must output a Slave
Address Byte. The 7 MSBs are the device identifiers. These
bits are “1101111” for the RTC registers and “1010111” for the
User SRAM.
The last bit of the Slave Address Byte defines a read or write
operation to be performed. When this R/W bit is a “1”, a read
operation is selected. A “0” selects a write operation (refer to
Figure 18).
After loading the entire Slave Address Byte from the SDA bus,
the ISL12022M compares the device identifier and device
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FN6668.4
December 18, 2008