ISL6568_06 Datasheet, PDF (24/29 Pages) Intersil Corporation – Two-Phase Buck PWM Controller with Integrated MOSFET Drivers for VRM9, VRM10, and AMD Hammer Applications

ISL6568
C₂ (OPTIONAL)
R_C ^CC
COMP
FB
ISL6568
R_FB
VDIFF
FIGURE 20. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6568 CIRCUIT
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately, there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator, by compensating the L-C
poles and the ESR zero of the voltage mode approximation,
yields a solution that is always stable with very close to ideal
transient performance.
Select a target bandwidth for the compensated system, f₀.
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of f₀
to the L-C pole frequency and the ESR zero frequency. For
each of the following three, there is a separate set of
equations for the compensation components.
Case 1:
---------1----------
2π LC
>
f₀
R_C
=
R_FB
2----π_{----f--0---V-----p---p--------L---C---}
0.66 V_{I N}
C_C
=
--------0---.--6---6----V----^I--^N----------
2πV_PPR_FBf₀
Case 2:
---------1----------
2π LC
≤
f₀
<
2----π^----C-----(^{-1-E-----S----R-----})
R_C
=
R_FB
V-----_P----P----(_--2----π_----)_--²_----f--0--²_{----L----C---}
0.66 V_IN
C_C
=
--------------------0----.-6----6---V-----^I--^N---------------------
(2π)² f₀₂ V_PPR_FB LC
(EQ. 29)
Case 3:
f₀ > _2----π----C-----₍-1-E-----S----R-----₎
R_C
=
R_FB
--------2----^π----f--⁰---V-----^p---^p---L---------
0.66 V_IN (ESR)
C_C
=
-0---.--6---6----V----^I--^N----⁽--E-----S----R-----⁾-------C---
2πV_PPR_FBf₀ L
In Equations 29, L is the per-channel filter inductance
divided by the number of active channels; C is the sum total
of all output capacitors; ESR is the equivalent series
resistance of the bulk output filter capacitance; and V_PP is
the peak-to-peak sawtooth signal amplitude as described in
the Electrical Specifications.
Once selected, the compensation values in Equations 29
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R_C. Slowly increase the
value of R_C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C_C will not need adjustment. Keep the value of C_C from
Equations 29 unless some performance issue is noted.
The optional capacitor C₂, is sometimes needed to bypass
noise away from the PWM comparator (See Figure 20).
Keep a position available for C₂, and be prepared to install a
high-frequency capacitor of between 22pF and 150pF in
case any leading edge jitter problem is noted.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step, ∆I,
the load-current slew rate, di/dt, and the maximum allowable
output-voltage deviation under transient loading, ∆V_MAX.
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output-
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
∆V ≈ (ESL) -d---i + (ESR) ∆I
dt
(EQ. 30)
The filter capacitor must have sufficiently low ESL and ESR
so that ∆V < ∆V_MAX.
24
FN9187.4
March 9, 2006