ISL6568_06 Datasheet, PDF (16/29 Pages) Intersil Corporation – Two-Phase Buck PWM Controller with Integrated MOSFET Drivers for VRM9, VRM10, and AMD Hammer Applications

ISL6568
VDIFF
+
V_{OFS RFB}
-
VREF
E/A
FB
I_OFS
R_OFS
OFS
ISL6568
GND
+
0.5V
-
-
1.5V
+
GND
VCC
FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
VDIFF
-
V_{OFS RFB}
+
VREF
E/A
FB
I_OFS
VCC
R_OFS
OFS
ISL6568
+
0.5V
-
-
1.5V
+
GND
VCC
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
Once the desired output offset voltage has been determined,
use the following formulas to set R_OFS:
For Positive Offset (connect R_OFS to GND):
R_OFS
=
-⁰---^.--⁵-----^×-----^R----^F----^B--
V_OFFSET
(EQ. 8)
For Negative Offset (connect R_OFS to VCC):
R_OFS
=
-¹---^.--⁵-----^×----^R-----^F----^B--
V_OFFSET
(EQ. 9)
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the core-
voltage regulator to do this by making changes to the VID
inputs. The core-voltage regulator is required to monitor the
DAC inputs and respond to on-the-fly VID changes in a
controlled manner, supervising a safe output voltage transition
without discontinuity or disruption.
The DAC mode the ISL6568 is operating in determines how
the controller responds to a dynamic VID change. When in
VRM10 mode the ISL6568 checks the VID inputs six times
every switching cycle. If a new code is established and it
stays the same for 3 consecutive readings, the ISL6568
recognizes the change and increments the reference.
Specific to VRM10, the processor controls the VID
transitions and is responsible for incrementing or
decrementing one VID step at a time. In VRM10 setting, the
ISL6568 will immediately change the reference to the new
requested value as soon as the request is validated; in
cases where the reference step is too large, the sudden
change can trigger overcurrent or overvoltage events.
In order to ensure the smooth transition of output voltage
during a VRM10 VID change, a VID step change smoothing
network is required for an ISL6568 based voltage regulator.
This network is composed of a 1kΩ internal resistor between
the output of DAC and the capacitor C_REF, between the REF
pin and ground. The selection of C_REF is based on the time
duration for 1 bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at 1
bit every T_VID, the relationship between C_REF and T_VID is
given by Equation 10.
C_REF = 0.004X T_VID
(EQ. 10)
As an example, for a VID step change rate of 5µs per bit, the
value of C_REF is 22nF based on Equation 10.
When running in VRM9 or AMD Hammer operation, the
ISL6568 responds slightly differently to a dynamic VID change
than when in VRM10 mode. In these modes the VID code can
be changed by more than a 1-bit step at a time. Once the
controller receives the new VID code it waits half of a phase
cycle and then begins slewing the DAC 12.5mV every phase
cycle, until the VID and DAC are equal. Thus, the total time
required for a VID change, t_DVID, is dependent on the
switching frequency (f_S), the size of the change (∆V_VID), and
the time required to register the VID change. The one-cycle
addition in the t_DVID equation is due to the possibility that the
VID code change may occur up to one full switching cycle
before being recognized. The approximate time required for a
ISL6568-based converter in AMD Hammer configuration
16
FN9187.4
March 9, 2006