ISL6568_06 Datasheet, PDF (21/29 Pages) Intersil Corporation – Two-Phase Buck PWM Controller with Integrated MOSFET Drivers for VRM9, VRM10, and AMD Hammer Applications

ISL6568
recovery charge, Q_rr, and the upper MOSFET r_DS(ON)
conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 17,
the required time for this commutation is t₁ and the
approximated associated power loss is P_UP,1.
P _{U P,1}
≈
V_IN


I--_M---
N
+
-I-^P--2--^P--_



t--_1--


2_
f_S
(EQ. 17)
At turn-on, the upper MOSFET begins to conduct and this
transition occurs over a time t₂. In Equation 18, the
approximate power loss is P_UP,2.
P_{UP, 2}
≈
V_IN


I--_M---
N
–
I--_{P-2---P--}



t--_2--


2_
f_S
(EQ. 18)
A third component involves the lower MOSFET reverse-
recovery charge, Q_rr. Since the inductor current has fully
commutated to the upper MOSFET before the lower-
MOSFET body diode can recover all of Q_rr, it is conducted
through the upper MOSFET across VIN. The power
dissipated as a result is P_UP,3.
P_UP,3 = V_IN Q_rr f_S
(EQ. 19)
Finally, the resistive part of the upper MOSFET is given in
Equation 20 as P_UP,4.
P_UP,4 ≈ r_DS(ON)



-I-^M---
N
2
d
+
-I-^P----^P--²-
12
(EQ. 20)
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 17, 18, 19 and 20. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of two drivers
in the controller package, the total power dissipated by both
drivers must be less than the maximum allowable power
dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of 125°C. The maximum allowable IC power
dissipation for the 5x5 QFN package is approximately 4W at
room temperature. See Layout Considerations paragraph for
thermal transfer improvement suggestions.
When designing the ISL6568 into an application, it is
recommended that the following calculation is used to
ensure safe operation at the desired frequency for the
selected MOSFETs. The total gate drive power losses,
P_{Qg_TOT}, due to the gate charge of MOSFETs and the
integrated driver’s internal circuitry and their corresponding
average driver current can be estimated with Equations 21
and 22, respectively.
P_{Qg_TOT} = P_{Qg_Q1} + P_{Qg_Q2} + I_Q • VCC
(EQ. 21)
P _{Q g _Q1}
=
3_--
2
•
Q_G
1
•
P
V
C
C
•
F_S
W
•
N_Q
1
•
N_PHASE
P_{Qg_Q2} = Q_G2 • PVCC • F_SW • N_Q2 • N_PHASE
(EQ. 22)
I_DR
=


3_--
2
•
Q_G
1
•
N_Q
1
+
Q_G
2
•
N_{Q2}
• N_PHASE • F_SW + I_Q
In Equations 21 and 22, P_{Qg_Q1} is the total upper gate drive
power loss and P_{Qg_Q2} is the total lower gate drive power loss;
the gate charge (Q_G1 and Q_G2) is defined at the particular gate
to source drive voltage PVCC in the corresponding MOSFET
data sheet; I_Q is the driver total quiescent current with no load
at both drive outputs; N_Q1 and N_Q2 are the number of upper
and lower MOSFETs per phase, respectively; N_PHASE is the
number of active phases. The I_Q*VCC product is the quiescent
power of the controller without capacitive load and is typically
75mW at 300kHz.
PVCC
BOOT
D
R_HI1
R_LO1
UGATE
C_GD
G
R_G1
R_GI1
C_GS
S
C_DS
Q1
PHASE
FIGURE 15. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
21
FN9187.4
March 9, 2006