ISL6308 Datasheet, PDF (23/27 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers

ISL6308
COMPENSATION BREAK FREQUENCY EQUATIONS
F_Z1
=
--------------¹----------------
2π ⋅ R₂ ⋅ C₁
F_Z2 = -₂---_π-----_â‹---₍---_R----₁-----+¹----_R-----₃---₎----_â‹---_C----₃--
F_P1
=
---------------------¹-----------------------
2π ⋅ R₂ ⋅ _C-^C----₁-¹----+^â‹---^C-_C----²-₂-
F_P2
=
--------------¹----------------
2π ⋅ R₃ ⋅ C₃
Figure 22 shows an asymptotic plot of the DC/DC
converter’s gain vs. frequency. The actual Modulator Gain
has a high gain peak dependent on the quality factor (Q) of
the output filter, which is not shown. Using the above
guidelines should yield a compensation gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F_P2
against the capabilities of the error amplifier. The closed loop
gain, G_CL, is constructed on the log-log graph of Figure 22
by adding the modulator gain, G_MOD (in dB), to the feedback
compensation gain, G_FB (in dB). This is equivalent to
multiplying the modulator transfer function and the
compensation transfer function and then plotting the
resulting gain.
F_Z1F_Z2 F_P1
F_P2
MODULATOR GAIN
COMPENSATION GAIN
CLOSED LOOP GAIN
OPEN LOOP E/A GAIN
20
log


RR-----21--_
0
20log ^d-----^M-----^A----^X------^â‹----V----I--N---
V_OSC
G_FB
G_CL
LOG
F_LC F_CE F₀
G_MOD
FREQUENCY
FIGURE 22. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin. The mathematical model
presented makes a number of approximations and is
generally not accurate at frequencies approaching or
exceeding half the switching frequency. When designing
compensation networks, select target crossover frequencies
in the range of 10% to 30% of the per-channel switching
frequency, F_SW.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is
usually the most costly (and often the largest) part of the
circuit. Output filter design begins with minimizing the cost of
this part of the circuit. The critical load parameters in
choosing the output capacitors are the maximum size of the
load step, ∆I, the load-current slew rate, di/dt, and the
maximum allowable output-voltage deviation under transient
loading, ∆V_MAX. Capacitors are characterized according to
their capacitance, ESR, and ESL (equivalent series
inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output-
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
∆V
≈
(ESL)
⋅
-d---i
dt
+
(ESR)
⋅
∆I
(EQ. 29)
The filter capacitor must have sufficiently low ESL and ESR
so that ∆V < ∆V_MAX.
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor ac ripple current (see Interleaving and
Equation 2), a voltage develops across the bulk capacitor
ESR equal to I_C,PP (ESR). Thus, once the output capacitors
are selected, the maximum allowable ripple voltage,
V_PP(MAX), determines the lower limit on the inductance.
L
≥ (ESR) ⋅
 ^{V I N}
–
N
⋅
V_O
U

T_
⋅
V_OUT
-----F----_S----_W------_â‹---V----_I--_N------_â‹---V----_P----_P---₍--_M-----_A----_X----₎----
(EQ. 30)
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
∆V_MAX. This places an upper limit on inductance.
23
FN9208.2
October 19, 2005