ISL6308 Datasheet, PDF (22/27 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers

ISL6308
C₂
COMP
R₂
C₁
-
FB
E/A ⁺
VREF
R₃
C₃
R₁
VDIFF
-
RGND
+
VSEN
PWM
CIRCUIT
OSCILLATOR
V_OSC
HALF-BRIDGE
DRIVE
V_OUT
V_IN
UGATE
PHASE
LGATE
L
DCR
C
ESR
ISL6308 EXTERNAL CIRCUIT
FIGURE 21. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The modulator transfer function is the small-signal transfer
function of V_OUT/V_COMP. This function is dominated by a DC
gain, given by d_MAXV_IN/V_OSC, and shaped by the output
filter, with a double pole break frequency at F_LC and a zero at
F_CE. For the purpose of this analysis, L and DCR represent
the individual channel inductance and its DCR divided by 3
(equivalent parallel value of the three output inductors), while
C and ESR represents the total output capacitance and its
equivalent series resistance.
F_LC=
-------------¹--------------
2π ⋅ L ⋅ C
F_CE=
----------------¹-----------------
2π ⋅ C ⋅ ESR
The compensation network consists of the error amplifier
(internal to the ISL6308) and the external R₁-R₃, C₁-C₃
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F₀; typically 0.1 to 0.3 of F_SW) and adequate phase
margin (better than 45 degrees). Phase margin is the difference
between the closed loop phase at F_0dB and 180°. The
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R₁, R₂, R₃, C₁, C₂, and
C₃) in Figure 20 and 21. Use the following guidelines for
locating the poles and zeros of the compensation network:
1. Select a value for R₁ (1kΩ to 5kΩ, typically). Calculate
value for R₂ for desired converter bandwidth (F₀).
R₂
=
---^V-----^O----^S----^C-----^â‹---^R-----¹----^â‹---^F----⁰-----
d_MAX ⋅ V_IN ⋅ F_LC
If setting the output voltage to be equal to the reference
set voltage as shown in Figure 21, the design procedure
can be followed as presented. However, when setting the
output voltage via a resistor divider placed at the input of
the differential amplifier (as shown in Figure 6), in order
to compensate for the attenuation introduced by the
resistor divider, the obtained R₂ value needs be
multiplied by a factor of (R_P+R_S)/R_P. The remainder of
the calculations remain unchanged, as long as the
compensated R₂ value is used.
2. Calculate C₁ such that F_Z1 is placed at a fraction of the F_LC,
at 0.1 to 0.75 of F_LC (to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F_CE/F_LC, the lower the F_Z1
frequency (to maximize phase boost at F_LC).
C₁
=
-----------------------¹-----------------------
2π ⋅ R₂ ⋅ 0.5 ⋅ F_LC
3. Calculate C₂ such that F_P1 is placed at F_CE.
C₂ = -₂---_π-----_â‹---_R-----₂----_â‹---_C-^C----₁-¹---_â‹---_F----_C----_E-----–-----₁-
4. Calculate R₃ such that F_Z2 is placed at F_LC. Calculate C₃
such that F_P2 is placed below F_SW (typically, 0.5 to 1.0
times F_SW). F_SW represents the per-channel switching
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F_P2 lower in
frequency helps reduce the gain of the compensation
network at high frequency, in turn reducing the HF ripple
component at the COMP pin and minimizing resultant
duty cycle jitter.
R₃
=
--------^R-----¹--------
F_{----S----W---- – 1}
F_LC
C₃
=
-----------------------¹-------------------------
2π ⋅ R₃ ⋅ 0.7 ⋅ F_SW
It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G_MOD), feedback
compensation (G_FB) and closed-loop response (G_CL):
G_MOD(f)
=
-^d---^M-----^A----^X-----^â‹---^V----^I--^N--
V_OSC
⋅
-------------------------------¹-----+-----^s---⁽---^f--⁾---^â‹---^E-----^S----^R------^â‹---^C----------------------------------
1 + s(f) ⋅ (ESR + DCR) ⋅ C + s²(f) ⋅ L ⋅ C
G_FB(f) = -_s---₍-¹-_f---₎-+--_â‹---^sR---⁽--₁-^f--⁾-_â‹--^â‹-₍--^RC-----²¹----^â‹_+---^C--_C---¹--₂----₎ ⋅
⋅ ------------------------------¹-----+-----^s---⁽---^f--⁾---^â‹---⁽---^R----¹-----+-----^R----³----⁾---^â‹---^C-----³-------------------------------
(1
+
s
(
f
)
⋅
R₃
⋅
C₃
)
⋅

1

+
s
(
f
)
⋅
R₂
⋅



C^-C----₁^{-1----+-⋅--C-}C^----2-₂^-_{}



G_CL(f) = G_MOD(f) ⋅ G_FB(f) _{where, s(f) = 2π ⋅ f ⋅ j}
22
FN9208.2
October 19, 2005