ISL6308 Datasheet, PDF (14/27 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers

ISL6308
VDIFF
-
V_{OFS R1}
+
VREF
E/A
FB
I_OFS
VCC
R_OFS
OFS
ISL6308
+
0.5V
-
-
1.5V
+
GND
VCC
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
Once the desired output offset voltage has been determined,
use the following formulas to set R_OFS:
For Positive Offset (connect R_OFS to GND):
R_OFS
=
----⁰---^.--⁵-----^â‹---^R----¹-----
V_OFFSET
(EQ. 9)
For Negative Offset (connect R_OFS to VCC):
R_OFS
=
----¹---^.--⁵-----^â‹---^R----¹-----
V_OFFSET
(EQ. 10)
Advanced Adaptive Zero Shoot-Through Deadtime
Control (Patent Pending)
The integrated drivers incorporate a unique adaptive
deadtime control technique to minimize deadtime, resulting
in high efficiency from the reduced freewheeling time of the
lower MOSFET body-diode conduction, and to prevent the
upper and lower MOSFETs from conducting simultaneously.
This is accomplished by ensuring either rising gate turns on
its MOSFET with minimum and sufficient delay after the
other has turned off.
During turn-off of the lower MOSFET, the PHASE voltage is
monitored until it reaches a -0.3V/+0.8V trip point for a
forward/reverse current, at which time the UGATE is
released to rise. An auto-zero comparator is used to correct
the r_DS(ON) drop in the phase voltage preventing false
detection of the -0.3V phase level during r_DS(ON) conduction
period. In the case of zero current, the UGATE is released
after 35ns delay of the LGATE dropping below 0.5V. During
the phase detection, the disturbance of LGATE falling
transition on the PHASE node is blanked out to prevent
falsely tripping. Once the PHASE is high, the advanced
adaptive shoot-through circuitry monitors the PHASE and
UGATE voltages during a PWM falling edge and the
subsequent UGATE turn-off. If either the UGATE falls to less
than 1.75V above the PHASE or the PHASE falls to less than
+0.8V, the LGATE is released to turn on.
Internal Bootstrap Device
All three integrated drivers feature an internal bootstrap
schottky diode. Simply adding an external capacitor across
the BOOT and PHASE pins completes the bootstrap circuit.
The bootstrap function is also designed to prevent the
bootstrap capacitor from overcharging due to the large
negative swing at the PHASE node. This reduces voltage
stress on the boot to phase pins.
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 5V and its capacitance value can be
chosen from the following equation:
C_B
O
O
T
_CAP
≥
----------^Q-----^G----^A----^T---^E-----------
∆ V_{B O O T _CAP}
Q_GATE=
Q_{-----G-----1----}•_--P_----V_-----C_----C_---
V_GS1
•
N
Q
1
(EQ. 11)
where Q_G1 is the amount of gate charge per upper MOSFET
at V_GS1 gate-source voltage and N_Q1 is the number of
control MOSFETs. The ∆V_{BOOT_CAP} term is defined as the
allowable droop in the rail of the upper gate drive. Figure 10
shows the boot capacitor ripple voltage as a function of boot
capacitor value and total upper MOSFET gate charge.
1.6
1.4
1.2
1.
0.8
0.6
0.4
0.2 _20nC
Q_GATE = 100nC
50nC
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
∆V_{BOOT_CAP} (V)
FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Gate Drive Voltage Versatility
The ISL6308 provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The controller
ties the upper and lower drive rails together. Simply applying
a voltage from 5V up to 12V on PVCC sets both gate drive
rail voltages simultaneously.
14
FN9208.2
October 19, 2005