ISL6308 Datasheet, PDF (19/27 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers

ISL6308
P_{Qg_TOT} = P_{Qg_Q1} + P_{Qg_Q2} + I_Q ⋅ VCC
P _{Q g _Q1}
=
3_--
2
⋅
Q_G1
⋅
P
V
C
C
⋅
F_S
W
⋅
N_Q
1
⋅
N_P
H
A
S
E
P_{Qg_Q2} = Q_G2 ⋅ PVCC ⋅ F_SW ⋅ N_Q2 ⋅ N_PHASE
(EQ. 20)
(EQ. 21)
I_DR
=


3_--
2
•
Q_G1
•
N_Q1
+
Q_G2
•
N_{Q2}
• N_PHASE • F_SW + I_Q
In Equations 20 and 21, P_{Qg_Q1} is the total upper gate drive
power loss and P_{Qg_Q2} is the total lower gate drive power
loss; the gate charge (Q_G1 and Q_G2) is defined at the
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; I_Q is the driver total
quiescent current with no load at both drive outputs; N_Q1
and N_Q2 are the number of upper and lower MOSFETs per
phase, respectively; N_PHASE is the number of active
phases. The I_Q*VCC product is the quiescent power of the
controller without capacitive load and is typically 75mW at
300kHz.
PVCC
BOOT
D
R_HI1
R_LO1
UGATE
C_GD
G
R_G1
R_GI1
C_GS
S
C_DS
Q1
PHASE
FIGURE 15. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
and R_G2) and the internal gate resistors (R_GI1 and R_GI2) of
the MOSFETs. Figures 15 and 16 show the typical upper
and lower gate drives turn-on transition path. The total power
dissipation in the controller itself, P_DR, can be roughly
estimated as:
P_DR = P_{DR_UP} + P_{DR_LOW} + P_BOOT + (I_Q • VCC) ^{(EQ. 22)}
P_BOOT
=
-^P----^Q----^g----^_---^Q----¹-
3
P _{D R _UP}
=



-_R----_H----_I--₁--^R---+--^H--_R--^I--¹-_E----_X----_T---₁--
+
-_R----_L---_O-----₁^R----+-^L---^O-_R----¹-_E----_X----_T---₁- _{}
• ^P-----^Q----^g----^_--^Q-----¹-
3
P _{D R _LOW}
=



-_R----_H----_I--₂--^R---+--^H--_R--^I--²-_E----_X----_T---₂--
+
R^-----_L^---_O^-----₂^{R----+-L---O-}R^----2-_E^----_X^----_T^---₂^- _{}
•
P_{-----Q----g----_--Q-----2-}
2
R_EXT1
=
R_G
1
+
R_{-----G-----I-1--}
N_Q1
R_EXT2
=
R_G
2
+
R_{-----G-----I-2--}
N_Q2
Current Balancing Component Selection
The ISL6308 senses the channel load current by sampling
the voltage across the lower MOSFET r_DS(ON), as shown in
Figure 17. The ISEN pins are denoted ISEN1, ISEN2, and
ISEN3. The resistors connected between these pins and the
respective phase nodes determine the gains in the channel
current balance loop.
Select values for these resistors based on the room
temperature r_DS(ON) of the lower MOSFETs; the full load
operating current, I_FL; and the number of phases, N using
Equation 23.
R_ISEN
=
5-r--^D-0---S--⋅^{--(-1-O--0---N-–--6-)- â‹}
I--_F----L-
N
(EQ. 23)
PVCC
R_HI2
R_LO2
LGATE
C_GD
G
R_G2
R_GI2
C_GS
S
D
C_DS
Q2
FIGURE 16. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance, P_{DR_UP}, the lower drive path resistance,
P_{DR_UP}, and in the boot strap diode, P_BOOT. The rest of the
power will be dissipated by the external gate resistors (R_G1
V_IN
CHANNEL N
UPPER MOSFET
I_L
ISEN(n)
ISL6308
R_ISEN
CHANNEL N
LOWER MOSFET
-
ILx rDS_(ON)
+
FIGURE 17. ISL6308 INTERNAL AND EXTERNAL CURRENT-
SENSING CIRCUITRY
In certain circumstances, it may be necessary to adjust the
value of one or more ISEN resistors. When the components
of one or more channels are inhibited from effectively
19
FN9208.2
October 19, 2005