ISL6144_14 Datasheet, PDF (23/30 Pages) Intersil Corporation – High Voltage ORing MOSFET Controller

ISL6144
This shows that worst-case failure scenario has to be
accounted for when choosing the ORing MOSFET. In both
cases, more than one ORing MOSFET/diode has to be
paralleled on each feed. Using parallel devices reduces
power dissipation per device and limits the junction
temperature rise to acceptable safe levels. Another
alternative is to choose a MOSFET with lower r_DS(ON)
(Refer to Tables 1 and 2 for some examples).
If parallel MOSFETs are used on each feed, make sure to
use the same part number. Also it is preferable to have parts
from the same lot to insure load sharing between these
paralleled devices.
The final choice of the N-Channel ORing MOSFET depends
on the following aspects:
• Voltage Rating: The drain-source breakdown voltage
V_DSS has to be higher than the maximum input voltage,
including transients and spikes. Also, the gate to source
voltage rating has to be considered. The ISL6144
maximum Gate charge voltage is 12V. Make sure the used
MOSFET has a maximum V_GS rating >12V.
• Power Losses: In this application, the ORing MOSFET is
used as a series pass element, which is normally fully
enhanced at high load currents. Switching losses are
negligible. The major losses are conduction losses, which
depend on the value of the on-state resistance of the
MOSFET r_DS(ON), and the per feed load current. For an
N + 1 redundant system with perfect current sharing, the
per feed MOSFET losses are:
P_loss(FET)
=
⎛
⎝
I_{--NL----O--+--A---1-D--⎠⎞}
2
⋅
r_D
S
(
O
N
)
(EQ. 14)
• The final MOSFET selection has to be based on the worse
case current when the system is reduced to N parallel
supplies due to a permanent failure of one unit. The
remaining units have to provide the full load current. In this
case, losses across each remaining ORing MOSFET
become Equation 15:
P_loss(FET)
=
⎛
⎝
I_{--L----O-N---A----D--⎠⎞}
2
⋅
r_D
S
(
ON)
(EQ. 15)
• In the particular cases illustrated in the previous examples
of Figures 29 and 30 with N = 1, each of the two ORing
feeds have to be able to handle the full load current.
• The MOSFET’s r_DS(ON) value also depends on junction
temperature; a curve showing this relationship is usually
part of any MOSFET’s data sheet. The increase in the
value of the r_DS(ON) over-temperature has to be taken into
account.
• Current handling capability, steady state and peak, are
also two important parameters that must be considered.
The limitation on the maximum allowable drain current
comes from limitation on the maximum allowable device
junction temperature. The thermal board design has to be
able to dissipate the resulting heat without exceeding the
MOSFET’s allowable junction temperature.
Suppose P_Loss = 1W in a D2PAK MOSFET, junction to
ambient thermal resistance R_θJA = +43°C/W (with 1 inch²
copper pad area), T_JMAX = +175°C, r_DS(ON) = 4.5mΩ,
maximum ambient board temperature = +85°C.
We need to make sure that the MOSFET’s junction
temperature during operation does not exceed the maximum
allowable device junction temperature.
T_J = T_{A_max} + P_Loss • R_θJA
T_J = +85°C+1W. +43°C/W = +128°C
T_J < T_JMAX
In the example of Figure 30 with a load of 32A, at least 3
MOSFETs with r_DS(ON) = 4.5mΩ are paralleled to limit the
dissipation to below 1W and operate with safe junction
temperature.
Tables 1 and 2 show MOSFET selection for some typical
applications with different input voltages and load currents in
a 1 + 1 redundant power system (a maximum of 1W of
power dissipation across each MOSFET is assumed).
For a 48V Input:
TABLE 1. INPUT VOLTAGE = 48V
I_{Load_Max}
8A
MOSFET PART NUMBER
FDB3632 (Note 14)
SUM110N10-08 (Note 15)
N (Note 13)
1
1
16A
FDB3632 (Note 14)
2
SUM110N10-08
2
FDB045AN08A0 (Note 16)
1
32A
FDB3632 (Note 14)
4
SUM110N10-08
4
FDB045AN08A0
3
NOTES:
13. Number of parallel MOSFETs per feed
14. V_DSS = 100V;I_D = 80A; r_DS(ON) = 9mΩ
15. V_DSS = 100V; I_D = 110A; r_DS(ON) = 9.5mΩ
16. V_DSS = 75V; I_D = 80A; r_DS(ON) = 4.5mΩ
23
FN9131.7
October 6, 2011