ISL6144_14 Datasheet, PDF (2/30 Pages) Intersil Corporation – High Voltage ORing MOSFET Controller

ISL6144
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6144IVZA (Note 1)
ISL61 44IVZ
-40 to +105
16 Ld TSSOP
M16.173
ISL6144IRZA (Note 1)
ISL6144 IRZ
-40 to +105
20 Ld 5x5 QFN
L20.5x5
ISL6441EVAL1Z
Evaluation Platform
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6144. For more information on MSL please see techbrief TB363.
Pinouts
ISL6144
(16 LD TSSOP)
TOP VIEW
ISL6144
(20 LD 5x5 QFN)
TOP VIEW
GATE 1
VIN 2
HVREF 3
NC ⁴
NC ⁵
NC ⁶
NC ⁷
GND ⁸
16 VOUT
15 COMP
14 VSET
13 NC
12 NC
11 NC
10 NC
9 FAULT
20 19 18 17 16
VIN 1
HVREF 2
NC 3
NC 4
NC 5
15 VOUT
14 COMP
13 VSET
12 NC
11 NC
6 7 8 9 10
Pin Descriptions
TSSOP
PIN #
1
2
3
QFN
PIN #
19
1
2
SYMBOL
FUNCTION
DESCRIPTION
GATE External FET Gate Drive
Allows active control of external N-Channel FET gate to perform ORing function.
VIN Power Supply Connection
Chip bias input. Also provides a sensing node for external FET control.
HVREF Chip High Voltage Reference Low side of floating high voltage reference for all of the HV chip circuitry.
8
7
GND Chip Ground Reference
Chip ground reference point.
9
9
FAULT Fault Output
Provides an open drain active low output as an indication that a fault has
occurred: GATE is OFF (GATE < V_IN + 0.37V) or other types of faults
resulting in V_IN - V_OUT > 0.41V.
14
13
VSET Low Side Connection for
Resistor connected to COMP provides adjustable “Vd - Vs” trip level along
Trip Level
with pin COMP.
15
14
COMP High Side Connection for HS Resistor connected to V_OUT provides sense point for the adjustable Vd - Vs
Comparator Trip Level
trip level along with pin VSET.
16
15
4, 5, 6, 7,
10, 11,
12, 13
3, 4, 5, 6, 8,
10, 11, 12,
16, 17,
18, 20
VOUT
NC
Chip Bias and Load
Connection
No Connection
Provides the second sensing node for external FET control and chip output
bias.
2
FN9131.7
October 6, 2011