ISL78201 Datasheet, PDF (22/23 Pages) Intersil Corporation – 40V 2.5A Regulator with Integrated High-side MOSFET for Synchronous Buck or Boost Buck Converter

ISL78201
Layout Suggestions
1. Put the input ceramic capacitors as close to the IC VIN pin and
power ground connecting to the power MOSFET or diode.
Keep this loop (input ceramic capacitor, IC V_IN pin and
MOSFET/diode) as tiny as possible to achieve the least
voltage spikes induced by the trace parasitic inductance.
2. Put the input aluminum capacitors close to IC VIN pin.
3. Keep the phase node copper area small but large enough to
handle the load current.
4. Put the output ceramic and aluminum capacitors also close
to the power stage components.
5. Put vias (20 recommended) in the bottom pad of the IC. The
bottom pad should be placed in the ground copper plane with
an area as large as possible in multiple layers to effectively
reduce the thermal impedance.
6. Place the 4.7µF ceramic decoupling capacitor at the VCC pin
and as close as possible to the IC. Put multiple vias (≥3) close
to the ground pad of this capacitor.
7. Keep the bootstrap capacitor close to the IC.
8. Keep the LGATE drive trace as short as possible and try to
avoid using a via in the LGATE drive path to achieve the lowest
impedance.
9. Place the positive voltage sense trace close to the load for
tighter regulation.
10. Place all the peripheral control components close to the IC.
.
FIGURE 38. PCB VIA PATTERN
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
CHANGE
March 31, 2015
FN8615.1 On page 6, updated Charged Device Model test method from “JESD22-C101E” to “AEC-Q100-11”.
February 18, 2014 FN8615.0 Initial Release
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FN8615.1
March 31, 2015