ISL78201 Datasheet, PDF (21/23 Pages) Intersil Corporation – 40V 2.5A Regulator with Integrated High-side MOSFET for Synchronous Buck or Boost Buck Converter

ISL78201
Phase margin: 45°
The compensator design procedure is as follows:
1. Position _CZ2 and _CP to derive R3 and C3.
Put the compensator zero _CZ2 at (1 to 3)/(R_oC_o)
_cz2
=
------³-------
R_oC_o
(EQ. 30)
Put the compensator pole _CP at ESR zero or 0.35 to 0.5 times
of switching frequency, whichever is lower. In all-ceramic-cap
design, the ESR zero is normally higher than half of the switching
frequency. R3 and C3 can be derived as following:
Case A: ESR zero
---------¹-----------
2R_cC_o
less than (0.35 to 0.5)f_s
C₃
=
R_-----o---C_{----o----–----}3_----R_----c---C_----o-
3R₁
(EQ. 31)
R₃ = -_R--³--_o--^R--–--^c--₃-^R---_R-¹---_c-
Case B: ESR zero
---------¹-----------
2R_cC_o
larger than (0.35 to 0.5)f_s
C₃
=
0_----._-3_----3_----R_----o---C_----o---f_{--s----–-----}0_---._--4_---6_--
f_s
R
1
R₃ = -₀---_.-₇----₃----_R----_o^R---_C-¹---_o---_f--_s----–-----₁--
Case C: Derive at R2 and C1.
(EQ. 32)
(EQ. 33)
(EQ. 34)
The loop gain L_v(S) at cross over frequency of f_c has unity gain.
Therefore, C1 is determined by Equation 35.
C₁
=
-^--^R----¹-----+-----^R----³---^---^C---³--
2
f_c
R_t
R₁
C
o
(EQ. 35)
The compensator zero _CZ1 can boost the phase margin and
bandwidth. To put _CZ1 at 2 times of cross cover frequency f_c is a
good start point. It can be adjusted according to specific design.
R1 can be derived from Equation 36.
R₂
=
---------¹---------
4f_cC₁
(EQ. 36)
Example: V_IN = 12V, V_o = 5V, I_o = 2A, f_s = 500kHz,
C_o = 60µF/3m, L = 10µH, R_t = 0.20V/A, f_c = 50kHz,
R₁ = 105k, R_BIAS = 20k.
Select the crossover frequency to be 35kHz. Since the output
capacitors are all ceramics, use Equations 33 and 34 to derive
R3 to be 20k and C3 to be 470pF.
Then use Equations 35 and 36 to calculate C₁ to be 180pF and
R₂ to be 12.7k. Select 150pF for C₁ and 15k for R₂.
There is approximately 30pF parasitic capacitance between
COMP to FB pins that contributes to a high frequency pole. Any
extra external capacitor is not recommended between COMP and
FB.
Figure 37 shows the simulated bode plot of the loop. It is shown
that it has 26kHz loop bandwidth with 70° phase margin and
-28dB gain margin.
80
60
40
20
0
-20
-40
-60
100
LOOP GAIN
1k
10k
100k
1M
FREQUENCY (Hz)
PHASE MARGIN
180
160
140
120
100
80
60
40
20
0100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 37. SIMULATED LOOP BODE PLOT
Note in applications where the PFM mode is desired especially
when type III compensation network is used, the value of the
capacitor between the COMP pin and the FB pin (not the
capacitor in series with the resistor between COMP and FB)
should be minimal to reduce the noise coupling for proper PFM
operation. No external capacitor between COMP and FB is
recommended at PFM applications.
In PFM mode operations, a RC filter from FB to ground (R in
series with C, connecting from FB to ground) may help to reduce
the noise effects injected to FB pin. The recommended values for
the filter is 499Ω to 1k for the R and 470pF for the C.
Loop Compensation Design for
2-Stage Boost Buck and
Single-Stage Buck Boost
For 2-stage boost buck and single-stage non-inverting buck boost
configurations, it’s highly recommended to use the iSim model
(The ISL78200 iSim model can be used to simulate ISL78201
and it’s available through internet) to evaluate the loop
bandwidth and phase margin.
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FN8615.1
March 31, 2015