ISL78201 Datasheet, PDF (18/23 Pages) Intersil Corporation – 40V 2.5A Regulator with Integrated High-side MOSFET for Synchronous Buck or Boost Buck Converter

ISL78201
PGOOD
The PGOOD pin is output of an open drain transistor (refer to at
“Block Diagram” on page 4). An external resistor is required to be
pulled up to VCC for proper PGOOD function. At startup, PGOOD
will be turned HIGH (internal PGOOD open drain transistor is
turned off) with 128 cycles delay after soft start is finished (soft
start ramp reaches 1.02V) and FB voltage is within OV/UV
window (90%REF<FB<110%REF).
At normal operation, PGOOD will be pulled low with 1 cycle
(minimum) and 6 cycles (maximum) delay if any of the OV (110%)
or UV (90%) comparator is tripped. The PGOOD will be released
HIGH with 128 cycles delay after FB recovers to be within OV/UV
window (90%REF<FB<110%REF). When EN is pulled low or VCC is
below POR, PGOOD is pulled low with no delay.
In the case when the PGOOD pin is pulled up by external bias
supply instead of VCC of itself, when the part is disabled, the
internal PGOOD open drain transistor is off, the external bias
supply can charge PGOOD pin HIGH. This should be known as false
PGOOD reporting. At start-up when VCC rise from 0, PGOOD will be
pulled low when VCC reaches 1V. After EN pulled low and VCC
falling, PGOOD internal open drain transistor will open with high
impedance when VCC falls below 1V. The time between EN pulled
low and PGOOD OPEN depends on the VCC falling time to 1V.
Fault Protection
Overcurrent Protection
The overcurrent function protects against any overload condition
and output shorts at worst case, by monitoring the current
flowing through the upper MOSFET.
There are 2 current limiting thresholds. The first one, I_OC1, is to
limit the high-side MOSFET peak current cycle-by-cycle. The
current limit threshold is set to default at 3.6A with the ILIMIT pin
connected to GND or VCC, or left open. The current limit threshold
can also be programmed by a resistor, R_LIM, at the ILIMIT pin to
ground. Use Equation 14 to calculate the resistor.
R_LIM = -_I-_O----_C----_³--_A-⁰---_-⁰---+⁰----⁰⁰---⁰-_.-₀----₁---₈--
(EQ. 14)
Note that with the lower R_LIM, I_OC1 is higher. The usable resistor
value range to program OC1 peak current threshold is 40kΩ
to 330kΩ. R_LIM value out of this range is not recommended.
320
300
280
260
240
220
200
180
160
140
120
100
80
60
40 ₀
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0
I_OC1 (A)
FIGURE 34. R_LIM vs I_OC1
The second current protection threshold, I_OC2, is 15% higher
than I_OC1 mentioned above. At the instant the high-side MOSFET
current reaches I_OC2, the PWM shuts off after a 2 cycle delay and
the IC enters hiccup mode. In hiccup mode, the PWM is disabled
for a dummy soft-start duration equal to 5 regular soft-start
periods. After this dummy soft-start cycle, the true soft-start cycle
is attempted again. The I_OC2 offers a robust and reliable
protection against worst case conditions.
The frequency fold back is implemented for the ISL78201. When
overcurrent limiting, the switching frequency is reduced to
proportional to the output voltage in order to keep the inductor
current under the limit threshold during overload condition. The
low limit of frequency under frequency foldback is 40kHz.
Overvoltage Protection
If the voltage detected on the FB pin is over 110% or 120% of
reference, the high-side and low-side driver shuts down
immediately and keep off until FB voltage drops to 0.8V. When
the FB voltage drops to 0.8V, the drivers are released ON. 110%
OVP is off at soft-start and becomes active after soft-start is
done. 120% OVP is active before and after soft-start.
Thermal Protection
The ISL78201 PWM will be disabled if the junction temperature
reaches +160°C. There is +20°C hysteresis for OTP. The part will
restart after the junction temperature drops below +140°C.
Component Selections
The ISL78200 iSim model is available on the web and can be
used to simulate the operating behaviors to assist the design.
Output Capacitors - Buck
An output capacitor is required to filter the inductor current.
Output ripple voltage and transient response are 2 critical factors
when considering output capacitance choice. The current mode
control loop allows the usage of low ESR ceramic capacitors and
thus smaller board layout. Electrolytic and polymer capacitors
may also be used.
Additional consideration applies to ceramic capacitors. While they
offer excellent overall performance and reliability, the actual in-
circuit capacitance must be considered. Ceramic capacitors are
rated using large peak-to-peak voltage swings and with no DC bias.
In the DC/DC converter application, these conditions do not reflect
reality. As a result, the actual capacitance may be considerably
lower than the advertised value. Consult the manufacturers data
sheet to determine the actual in-application capacitance. Most
manufacturers publish capacitance vs DC bias so that this effect
can be easily accommodated. The effects of AC voltage are not
frequently published, but an assumption of ~20% further
reduction will generally suffice. The result of these considerations
can easily result in an effective capacitance 50% lower than the
rated value. Nonetheless, they are a very good choice in many
applications due to their reliability and extremely low ESR.
The following equations allow calculation of the required
capacitance to meet a desired ripple voltage level. Additional
capacitance may be used.
Submit Document Feedback 18
FN8615.1
March 31, 2015