ISL78201 Datasheet, PDF (17/23 Pages) Intersil Corporation – 40V 2.5A Regulator with Integrated High-side MOSFET for Synchronous Buck or Boost Buck Converter

ISL78201
(V_IN *I_IN = V_OUT * I_OUT / Efficiency). If the design is to achieve the
low input operation with full load, the inductor and MOSFET have
to be selected to have enough current ratings to handle the high
current appearing at boost input. The boost inductor current are
the same with the boost input current, which can be estimated in
Equation 8, where P_OUT is the output power, VBAT is the boost
input voltage, and EFF is the estimated efficiency of the whole
boost and buck stages.
IL_IN
=
--------^P----^O----^U----^T--------
VBAT  EFF
(EQ. 8)
Based on the same concerns of boost input current, the start-up
sequence must follow the rule that the IC is enabled after the
boost input voltage rise above a certain level. The shutdown
sequence must follow the rule that the IC is disabled first before
the boost input power source is turned off. At boost mode
applications where there is no external control signal to
enable/disable the IC, an external input UVLO circuit must be
implemented for the start-up and shutdown sequence.
PFM is not available in boost mode.
Non-inverting Single Inductor Buck Boost
Converter Operation
In “Typical Application Schematic III - Boost Buck Converters” on
page 5, schematic (b) shows non-inverting single inductor buck
boost configuration. The recommended setting is to use resistor
divider 1MΩ and 130kΩ (as shown in “Typical Application
Schematic III - Boost Buck Converters” on page 5 (b) connecting
from VCC to both EXT_BOOST and AUXVCC pins (EXT_BOOST and
AUXVCC pin are directly connected). In this way, the EXT_BOOST
pin voltage is a fixed voltage 0.52V that is higher than the boost
mode detection threshold 0.2V to set IC in boost mode and lower
than the boost switching threshold 800mV to have boost being
constantly switching (during and after soft-start).
As the same in 2-stage boost buck mode, LGATE is switching ON
with the same phase of upper FETs switching ON, meaning both
upper and lower side FETs are ON and OFF at the same time with
the same duty cycle. When both FETs ON, input voltage charges
inductor current ramping up for duration of DT; when both FETs
OFF, inductor current is free wheeling through the 2 power diodes
to output, and output voltage discharge the inductor current
ramping down for (1-D)T (in CCM mode). The steady state DC
transfer function is:
V_OUT = _{1-------D–}-------D---  V_IN
(EQ. 9)
where V_IN is the input voltage, V_OUT is the buck boost output
voltage, D is duty cycle.
Another useful equation is to calculate the inductor DC current as
shown in Equation 10:
IL_DC = _{1-------1–}-------D---  I_OUT
(EQ. 10)
where IL_DC is the inductor DC current and I_OUT is the output DC
current.
Equation 10 says the inductor current is charging output only
during (1-D)T, which means inductor current has larger DC
current than output load current. So for this part with high side
FET integrated, the non-inverting buck boost configuration has
less load current capability compared with buck and 2-stage
boost buck configurations. Its load current capability depends
mainly on the duty cycle and inductor current.
Inductor ripple current can be calculated below:
IL_RIPPLE
=
-V----^O------^U----^T-----^---1-------^–------D------^---T---
L
(EQ. 11)
The inductor peak current is,
IL_PEAK
=
IL_DC
+
1---
2

IL_RIPPLE
(EQ. 12)
In power stage DC calculations, use Equation 9 to calculate D,
then use Equation 10 to calculate IL_DC. D and IL_DC are useful
information to estimate the high side FET’s power losses and
check if the part can meet the load current requirements..
1200
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0
0
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F_S (kHz)
FIGURE 33. R_FS vs FREQUENCY
Oscillator and Synchronization
The oscillator has a default frequency of 500kHz with the FS pin
connected to VCC, ground, or floating. The frequency can be
programmed to any frequency between 200kHz and 2.2MHz with
a resistor from the FS pin to GND.
R_FSk = -¹---⁴----⁵---⁰----⁰---⁰--_F---–_S----_-¹--_k-⁶--_H---^--_z-^F--_--^S----^--^k---^H-----^z----^
(EQ. 13)
The SYNC pin is bi-directional and it outputs the IC’s default or
programmed local clock signal when it’s free running. The IC
locks to an external clock injected to SYNC pin (external clock
frequency recommended to be 10% higher than the free running
frequency). The delay from the rising edge of the external clock
signal to the PHASE rising edge is half of the free running switching
period pulse 220ns, (0.5Tsw+220ns). The maximum external clock
frequency is recommended to be 1.6 of the free running frequency.
When the part enters PFM pulse skipping mode, the
synchronization function is shut off and also no clock signal
output in SYNC pin.
With the SYNC pins simply connected together, multiple
ISL78201s can be synchronized. The slave ICs automatically
have 180° phase shift respect to the master IC.
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FN8615.1
March 31, 2015