ISL70617SEH Datasheet, PDF (21/28 Pages) Intersil Corporation – High voltage process control

ISL70617SEH
There are four behaviors of current feedback amplifiers that
must be considered:
1. Frequency response increases with decreasing values of R_FB.
A comparison of the G = 100, -3db response (Figures 28 and
29) R_FB at 30.1kΩ vs 121kΩ shows almost a 4X decrease
from 2MHz to 0.5MHz.
2. Gain peaking tends to increase with decreasing values of R_FB
3. Wideband applications at gains less than 1 (Figures 28 and
29) can have high gain peaking resulting in high levels of
overshoot with pulsed input signals
4. Parasitic capacitance at the feedback resistor terminals
(+R_FB, -R_FB) and the Kelvin sense terminals (+R_FBSENSE,
-R_FBSENSE) will result in increasing levels of peaking and
transient response overshoot.
To minimize peaking, external PC parasitic capacitance should
be minimized as much as possible. The ISL70617SEH is
designed to be stable with PC board parasitic capacitance up to
20pF and feedback resistor values down to 30.1kΩ. At gains less
than 1, the maximum parasitic capacitance may have to be
limited further to avoid additional compensation.
Uncorrected gain peaking and high overshoot in the feedback
stage can cause loss of feedback loop stability if the transient
causes the feedback voltage to exceed the common-mode input
range of the feedback amplifier or the maximum linear range of
the feedback resistor R_FB. Corrective actions include increasing
the size of the feedback resistor (see Figure 49 on page 19) and
rescaling the input gain resistor R_IN, or adding input frequency
compensation described in the next section.
The penalty of increasing the R_FB (and R_IN rescaling) is increased
noise, so this is generally not the corrective action of choice.
AC Compensation Techniques
Input compensation with a low pass filter (Figure 51) can be an
effective way to block high frequency signals from the
differential amplifier inputs. It does not change the gain peaking
behavior of the feedback loop, but it does block signals from
creating overdrive instability. This method is useful after other
corrective measures have been implemented, and when there is
little control over the input signal frequency content.
DIFFERENTIAL
INPUT SIGNAL
COMMON-MODE
ERROR
R/2
C
R/2
TRACE
CAPACITANCE
IN- ^500Ω
IN+ ^500Ω
GND
FIGURE 51. INPUT DIFFERENTIAL LOW PASS FILTER AND
PARASITIC CAPACITANCE
Input Common-Mode Rejection
Considerations
The ISL70617SEH is capable of a very high level (110dB) of
CMRR performance from DC to as high as 1kHz for gains greater
than 100, (see Figures 38 and 39 on page 15). This high level of
performance over frequency is made possible by the high
common-mode input impedance (80GΩ) but requires careful
attention to the matching of the IN+ and IN- external impedances
to GND.
A mismatch in the series impedance in conjunction with parasitic
capacitance at the IN+, IN- terminals (Figure 51) will cause a
common-mode amplitude imbalance that will show up as a
differential input signal, rapidly degrading CMRR as the
common-mode frequency increases.
Maximum CMRR performance is achieved with attention to
balancing external components and attention to PC layout.
Layout Guidelines
The ISL70617SEH is a high precision device with wideband AC
performance. Maximizing DC precision requires attention to the
layout of the gain resistors. Achieving good AC response requires
attention to parasitic capacitance at the gain resistor terminals.
CMRR performance over frequency is ensured with symmetrical
component placement and layout of the input differential signals
to the IN+ and IN- terminals.
To ensure the highest DC precision, the location of the gain
resistors and PC trace connections to the Kelvin connections are
most important. Proper Kelvin connections remove trace
resistance errors so that the amplifier gain accuracy and gain
temperature coefficients are determined by the gain resistor
matching tolerance. Interconnect constraints preclude mounting
the gain resistors next to each other, so they should be located on
either side of the ISL70617SEH and as close to the device as
possible. The Kelvin connections are formed at the junction of
the sense pins (±R_INSENSE, ±R_FBSENSE) and the gain resistor
current drive terminals (±R_IN, ±R_FB). This junction should be
made at the terminal pads directly under the ends of each
resistor.
Reduced trace lengths that maintain DC accuracy are also
important for minimizing the capacitance that can degrade AC
stability. This is especially true at gains less than one.
Layout guidelines for high CMRR include matching trace lengths
and symmetrical component placement on the circuit that
connects the signal source to the IN+, IN- pins. This ensures
matching of the IN+ and IN- input impedances (Figure 51).
Power Supply Decoupling
Standard power supply decoupling consists of a single 0.1µF 50V
ceramic capacitor at the power supply terminals located as close
to the device as possible. In applications where the input and
output supplies are strapped to the same voltage (V_EE = V_EO,
V_CC = V_CO), the connection point should be as close to the device
as possible with a single 0.1µF 50V ceramic capacitor at the
junction. Applications using separate supplies require 0.1µF 50V
ceramic decoupling capacitors at each power supply terminal.
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FN8697.4
December 16, 2016