ISL70617SEH Datasheet, PDF (17/28 Pages) Intersil Corporation – High voltage process control

ISL70617SEH
Applications Information
“General Description” contains the ISL70617SEH functional and
performance objectives and description of operation.
“Designing with the ISL70617SEH” on page 18 contains the
application circuit design equations and guidelines for achieving
the desired DC and AC performance levels.
“Estimating Amplifier DC and Noise Performance” on page 22
provides equations for predicting DC offset voltage and noise of
the finished design.
General Description
The ISL70617SEH is an elaboration of the simpler
current-feedback approach. The G_Ms are implemented with two
external resistors and very high-gain amplifiers that impose input
and feedback voltages upon them. The amplifiers have gains
around ten million and linearize the transistors errors well below
the 10ppm level. The overall gain is (R_FB/R_IN). With very high
gain in the pseudo-G_Ms, the circuit adds little gain error and only
R_FB and R_IN set gain to the 10ppm level. Thus, only the matching
of the external resistors sets gain error and the cost of the
resistors can be tailored to the accuracy needed. Note that the
input stage is completely unaffected by output biasing, which is
the right thing for an instrumentation amplifier.
The ISL70617SEH instrumentation amplifier was developed to
accomplish the following:
• Provide a fully differential, rail-to-rail output for optimally
driving ADCs. Maximum differential voltage set by R_FB
(Equation 8 on page 18).
• Limit the output swing to prevent output overdrive
• Allow any gain, including attenuation
• Maximize gain accuracy by removing on-chip component
tolerances and external PC board parasitic resistance
• Enable user control of amplifier precision level with choice of
external resistor tolerance
• Maintain CMRR >100dB and remove CMRR sensitivity to gain
resistor tolerance
• Provide a level-shift interface from bipolar analog input signal
sources to unipolar and bipolar ADC output terminations
Functional Description
Figure 48 shows the functional block diagram for the
ISL70617SEH.
V_CC
0.1µF
IN-
500Ω
INPUT
STAGE
I1
I2
FEEDBACK
STAGE
I3
I4
OUTPUT
STAGE
A5
I1, I3
I2, I4
+-A6
V_CO
0.1µF
+V_OUT
-V_OUT
V_FB-
IN+
500Ω
+-A1
V_EE
0.1µF
+R_IN
+R_INSENSE
Q1 Q2
A2+-
100µA
I_S1 I_S2
+-A3
Q3 Q4
+
A4 _-
100µA
I_S3 I_S4
R_IN
-R_IN
-R_FB
R_FB
+R_FB
GND
-R_INSENSE -R_FBSENSE
GAIN RESISTORS AND
+R_FBSENSE
KELVIN CONNECTIONS
FIGURE 48. ISL70617SEH FUNCTIONAL BLOCK DIAGRAM
V_FB+
V_CMO
V_EO
0.1µF
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FN8697.4
December 16, 2016