82C37A_06 Datasheet, PDF (21/24 Pages) Intersil Corporation – CMOS High Performance Programmable DMA Controller

Timing Waveforms (Continued)
82C37A
S0
S11
S12
S13
S14
S21
S22
S23
S24
S11/SI
CLK
(33)
TCLSH
ADSTB
TFAAB (22)
TASS (11)
A0-A7
(34)
TCLSL
TFADB (24)
(33)
TCLSH
(7)
TAHS
(59) TRHSH
ADDRESS VALID
(5) TAFDB _TASS
(11)
(34)
TCLSL
TAHS
(7)
TWHSH
(60)
ADDRESS VALID
TAFDB
(5)
DB0-DB7
TFAC (23)
MEMR
TFAC (23)
A8-A15
TDCL
(15)
IN
(16) TDCTR
TAZRL _TIDS
(64)
(27)
A8-A15
(24)
TFADB _TOVD
TIDH (26) ⁽²⁹⁾
TDCTW (17)
TDCL
(15)
TDCL
(15)
OUT
MEMW
EOP
EXTENDED WRITE
(19) TEPH
TAK
(9)
TEPS (20)
EXT EOP
TEPW
(21)
TCLSH
(33)
TAFAB
(3)
TODH (28)
TAFC
(4)
TAFC
(4)
TAK
(9)
FIGURE 11. MEMORY-TO-MEMORY TRANSFER
CLK
READ
WRITE
READY
S2
S3
SW
(15)
TDCL
(15)
TDCL
(15)TDCL
EXTENDED WRITE
(31)TRH
(32)TRS
(31)
TRH
SW
(32)TRS
S4
(16)
TDCTR
(17)
TDCTW
FIGURE 12. READY
NOTE: READY must not transition during the specified setup and hold times.
21
FN2967.2
March 20, 2006