82C37A_06 Datasheet, PDF (1/24 Pages) Intersil Corporation – CMOS High Performance Programmable DMA Controller

®
Data Sheet
March 20, 2006
82C37A
FN2967.2
CMOS High Performance
Programmable DMA Controller
The 82C37A is an enhanced version of the industry standard
8237A Direct Memory Access (DMA) controller, fabricated
using Intersil’s advanced 2 micron CMOS process. Pin
compatible with NMOS designs, the 82C37A offers
increased functionality, improved performance, and
dramatically reduced power consumption. The fully static
design permits gated clock operation for even further
reduction of power.
The 82C37A controller can improve system performance by
allowing external devices to transfer data directly to or from
system memory. Memory-to-memory transfer capability is
also provided, along with a memory block initialization
feature. DMA requests may be generated by either hardware
or software, and each channel is independently
programmable with a variety of features for flexible
operation.
Features
• Compatible with the NMOS 8237A
• Four Independent Maskable Channels with
Autoinitialization Capability
• Cascadable to any Number of Channels
• High Speed Data Transfers:
- Up to 4MBytes/sec with 8MHz Clock
- Up to 6.25MBytes/sec with 12.5MHz Clock
• Memory-to-Memory Transfers
• Static CMOS Design Permits Low Power Operation
- ICCSB = 10µA Maximum
- ICCOP = 2mA/MHz Maximum
• Fully TTL/CMOS Compatible
• Internal Registers may be Read from Software
• Pb-Free Plus Anneal Available (RoHS Compliant)
The 82C37A is designed to be used with an external
address latch, such as the 82C82, to demultiplex the most
significant 8-bits of address. The 82C37A can be used with
industry standard microprocessors such as 80C286, 80286,
80C86, 80C88, 8086, 8088, 8085, Z80, NSC800, 80186 and
others. Multimode programmability allows the user to select
from three basic types of DMA services, and reconfiguration
under program control is possible even with the clock to the
controller stopped. Each channel has a full 64K address and
word count range, and may be programmed to autoinitialize
these registers following DMA termination (end of process).
Ordering Information
5MHz
PART
MARKING
PART NUMBER
8MHz
PART
MARKING
12.5MHz
PART
MARKING
PACKAGE
TEMP
RANGE
(°C)
PKG.
DWG. #
CP82C37A-5
CP82C37A-5 CP82C37A
CP82C37A-12
40 Ld PDIP
0 to +70 E40.6
IP82C37A-5
IP82C37A
IP82C37A-12
-40 to +85 E40.6
CS82C37A-5
CS82C37A*
CS82C37A CS82C37A-1296 CS82C37A-12 44 Ld PLCC 0 to +70 N44.65
CS82C37AZ (Note) CS82C37AZ
44 Ld PLCC
(Pb-Free)
0 to +70 N44.65
IS82C37A-5
IS82C37A
IS82C37A-12
44 Ld PLCC -40 to +85 N44.65
CD82C37A-5
CD82C37A
CD82C37A-12
40 Ld CERDIP 0 to +70 F40.6
ID82C37A-5
ID82C37A
ID82C37A-12
-40 to +85 F40.6
MD82C37A-5/B
MD82C37A/B
MD82C37A/B MD82C37A-12/B
-55 to +125 F40.6
5962-9054301MQA
5962-
9054302MQA
5962-
9054303MQA
SMD#
F40.6
MR82C37A-5/B
MR82C37A/B
MR82C37A-12/B
44 Pad CLCC -55 to +125 J44.A
5962-9054301MXA
5962-9054302MXA
5962-9054303MXA
SMD#
J44.A
*Add "96" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS
compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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