82C37A_06 Datasheet, PDF (14/24 Pages) Intersil Corporation – CMOS High Performance Programmable DMA Controller

82C37A
Figure 7 shows an application for a DMA system using the
82C37A DMA controller and the 80C286 Microprocessor.
In this application, the system clock comes from the 82C284
clock generator PCLK signal which is inverted to provide
proper READY setup and hold times to the DMA controller in
an 80C286 system. The Read and Write signals from the
DMA controller may be wired directly to the Read/Write
control signals from the 82C288 Bus Controller. The octal
latch for A8-A15 from the DMA controller’s data bus is on the
local 80C286 address bus so that memory chip selects may
still be generated during DMA transfers. The transceiver on
A0-A7 is controlled by AEN and is not necessary, but may be
used to drive a heavily loaded system address bus during
transfers. The data bus transceivers simply isolate the DMA
controller from the local microprocessor bus and allow
programming on the upper or lower half of the data bus.
80C286
A0-A23
D0-D15
READY
HLD
CLK
HLDA
82C288
IORC
IOWC
MRDC
MWTC
CLK
IOR
IOW
MEMR
MEMW
DECODE
CHIP SELECT
TO MEMORY/
PERIPHERALS
LATCH
A0 - A23
TRANSCEIVER
SYSTEM
BUS
D0 - D15
LATCH
STB
OE
TRANS-
CEIVER
D0-D7
V_CC
TRANS-
CEIVER
TRANSCEIVER
T/R
OE
AEN
MEMORY
MEMR
MEMW
MEMCS
I/O
DEVICE
DREQ
CS
IOR
IOW
DACK
82C284
CLK
PCLK
READY
AEN
ADSTB
HRQ
HLDA
CLK
READY
EOP D0-D7
82C37A
DREQ 0-3
A0-A7
IOR
IOW
MEMR
MEMW
DACK 0-3
IOR
IOW
MEMR
MEMW
TO CORRESPONDING
82C288 SIGNALS AND
MEMORY/PERIPHERALS
FIGURE 7. 80C286 DMA APPLICATION
14
FN2967.2
March 20, 2006