82C37A_06 Datasheet, PDF (2/24 Pages) Intersil Corporation – CMOS High Performance Programmable DMA Controller

82C37A
Pinouts
82C37A (PDIP/CERDIP)
TOP VIEW
IOR 1
IOW 2
MEMR 3
MEMW 4
NC 5
READY 6
HLDA 7
ADSTB 8
AEN 9
HRQ 10
CS 11
CLK 12
RESET 13
DACK2 14
DACK3 15
DREQ3 16
DREQ2 17
DREQ1 18
DREQ0 19
(GND) VSS 20
40 A7
39 A6
38 A5
37 A4
36 EOP
35 A3
34 A2
33 A1
32 A0
31 VCC
30 DB0
29 DB1
28 DB2
27 DB3
26 DB4
25 DACK0
24 DACK1
23 DB5
22 DB6
21 DB7
82C37A (CLCC/PLCC)
TOP VIEW
6 5 4 3 2 1 44 43 42 41 40
NC 7
39 A3
NC 8
38 A2
HLDA 9
37 A1
ADSTB 10
36 A0
AEN 11
35 VCC
HRQ 12
34 DB0
CS 13
33 DB1
CLK 14
32 DB2
RESET 15
31 DB3
DACK2 16
NC ₁₇
30 DB4
29 NC
18 19 20 21 22 23 24 25 26 27 28
Block Diagram
EOP
RESET
CS
READY
CLK
AEN
ADSTB
MEMR
MEMW
IOR
IOW
TIMING
AND
CONTROL
DREQ0 - ⁴
DREQ3
HLDA
HRQ
DACK0 - 4
DACK3
PRIORITY
ENCODER
AND
ROTATING
PRIORITY
LOGIC
DECREMENTOR
TEMP WORD
COUNT REG (16)
INC/DECREMENTOR
TEMP ADDRESS
REG (16)
16-BIT BUS
16-BIT BUS
READ BUFFER
READ WRITE BUFFER
BASE
ADDRESS
(16)
BASE
WORD
COUNT
(16)
CURRENT
ADDRESS
(16)
CURRENT
WORD
COUNT
(16)
WRITE
BUFFER
READ
BUFFER
IO
BUFFER
A0 - A3
OUTPUT
BUFFER
A4 - A7
COMMAND
CONTROL
D0 - D1
COMMAND
(8)
MASK
(4)
REQUEST
(4)
INTERNAL DATA BUS
IO
BUFFER
MODE
(4 x 6)
STATUS
(8)
TEMPORARY
(8)
2
FN2967.2
March 20, 2006